Datasheet LTC1416 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Low Power 14-Bit, 400ksps Sampling ADC |
| Pages / Page | 20 / 4 — POWER REQUIRE E TS The. denotes specifications which apply over the full … |
| File Format / Size | PDF / 338 Kb |
| Document Language | English |
POWER REQUIRE E TS The. denotes specifications which apply over the full operating temperature range,
Model Line for this Datasheet
Text Version of Document
LTC1416
W U POWER REQUIRE E TS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ISS Negative Supply Current ● 7 10 mA Nap Mode SHDN = 0V, CS = 0V 20 µA Sleep Mode SHDN = 0V, CS = 5V 15 µA PDISS Power Dissipation ● 70 100 mW Power Dissipation, Nap Mode SHDN = 0V, CS = 0V 4 6 mW Power Dissipation, Sleep Mode SHDN = 0V, CS = 5V 0.1 mW
W U TI I G CHARACTERISTICS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5, see Figures 15 to 21) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency ● 400 kHz tCONV Conversion Time ● 1.5 1.9 2.2 µs tACQ Acquisition Time (Note 9) ● 100 400 ns tACQ+CONV Acquisition + Conversion Time ● 2 2.5 µs t1 CS to RD Setup Time (Notes 9, 10) ● 0 ns t2 CS↓ to CONVST↓ Setup Time (Notes 9, 10) ● 10 ns t3 CS↓ to SHDN↓ Setup Time (Notes 9, 10) ● 10 ns t4 SHDN↑ to CONVST↓ Wake-Up Time CS = 0V (Note 10) 400 ns t5 CONVST Low Time (Notes 10, 11) ● 40 ns t6 CONVST to BUSY Delay CL = 25pF 25 ns ● 50 ns t7 Data Ready Before BUSY↑ (Note 9) 75 100 ns ● 50 ns t8 Delay Between Conversions (Note 10) ● 40 ns t9 Wait Time RD↓ After BUSY↑ ● – 5 ns t10 Data Access Time After RD↓ CL = 25pF 15 25 ns ● 35 ns CL = 100pF 20 35 ns ● 50 ns t11 Bus Relinquish Time 8 20 ns 0°C ≤ TA ≤ 70°C ● 25 ns – 40°C ≤ TA ≤ 85°C ● 30 ns t12 RD Low Time ● t10 ns t13 CONVST High Time ● 40 ns
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 7:
Integral nonlinearity is defined as the deviation of a code from a of a device may be impaired. straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
Note 2:
All voltage values are with respect to ground with DGND and AGND wired together unless otherwise noted.
Note 8:
Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 00 and
Note 3:
When these pin voltages are taken below VSS or above VDD, they 1111 1111 1111 11. will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup.
Note 9:
Guaranteed by design, not subject to test.
Note 4:
When these pin voltages are taken below V
Note 10:
Recommended operating conditions. SS, they will be clamped by internal diodes. This product can handle input currents greater than
Note 11:
The falling CONVST edge starts a conversion. If CONVST returns 100mA below VSS without latchup. These pins are not clamped to VDD. high at a critical point during the conversion it can create small errors. For
Note 5:
VDD = 5V, VSS = – 5V, fSAMPLE = 400kHz, tr = tf = 5ns unless best results ensure that CONVST returns high either within 900ns after the otherwise specified. start of the conversion or after BUSY rises.
Note 6:
Linearity, offset and full-scale specifications apply for a single- ended A + – IN input with AIN grounded. 4
W U POWER REQUIRE E TS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ISS Negative Supply Current ● 7 10 mA Nap Mode SHDN = 0V, CS = 0V 20 µA Sleep Mode SHDN = 0V, CS = 5V 15 µA PDISS Power Dissipation ● 70 100 mW Power Dissipation, Nap Mode SHDN = 0V, CS = 0V 4 6 mW Power Dissipation, Sleep Mode SHDN = 0V, CS = 5V 0.1 mW
W U TI I G CHARACTERISTICS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5, see Figures 15 to 21) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency ● 400 kHz tCONV Conversion Time ● 1.5 1.9 2.2 µs tACQ Acquisition Time (Note 9) ● 100 400 ns tACQ+CONV Acquisition + Conversion Time ● 2 2.5 µs t1 CS to RD Setup Time (Notes 9, 10) ● 0 ns t2 CS↓ to CONVST↓ Setup Time (Notes 9, 10) ● 10 ns t3 CS↓ to SHDN↓ Setup Time (Notes 9, 10) ● 10 ns t4 SHDN↑ to CONVST↓ Wake-Up Time CS = 0V (Note 10) 400 ns t5 CONVST Low Time (Notes 10, 11) ● 40 ns t6 CONVST to BUSY Delay CL = 25pF 25 ns ● 50 ns t7 Data Ready Before BUSY↑ (Note 9) 75 100 ns ● 50 ns t8 Delay Between Conversions (Note 10) ● 40 ns t9 Wait Time RD↓ After BUSY↑ ● – 5 ns t10 Data Access Time After RD↓ CL = 25pF 15 25 ns ● 35 ns CL = 100pF 20 35 ns ● 50 ns t11 Bus Relinquish Time 8 20 ns 0°C ≤ TA ≤ 70°C ● 25 ns – 40°C ≤ TA ≤ 85°C ● 30 ns t12 RD Low Time ● t10 ns t13 CONVST High Time ● 40 ns
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 7:
Integral nonlinearity is defined as the deviation of a code from a of a device may be impaired. straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
Note 2:
All voltage values are with respect to ground with DGND and AGND wired together unless otherwise noted.
Note 8:
Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 00 and
Note 3:
When these pin voltages are taken below VSS or above VDD, they 1111 1111 1111 11. will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup.
Note 9:
Guaranteed by design, not subject to test.
Note 4:
When these pin voltages are taken below V
Note 10:
Recommended operating conditions. SS, they will be clamped by internal diodes. This product can handle input currents greater than
Note 11:
The falling CONVST edge starts a conversion. If CONVST returns 100mA below VSS without latchup. These pins are not clamped to VDD. high at a critical point during the conversion it can create small errors. For
Note 5:
VDD = 5V, VSS = – 5V, fSAMPLE = 400kHz, tr = tf = 5ns unless best results ensure that CONVST returns high either within 900ns after the otherwise specified. start of the conversion or after BUSY rises.
Note 6:
Linearity, offset and full-scale specifications apply for a single- ended A + – IN input with AIN grounded. 4
