Datasheet LTC1420 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 12-Bit, 10Msps, Sampling ADC |
| Pages / Page | 20 / 7 — PIN FUNCTIONS. VDD (Pin 23):. CLK (Pin 26):. GND (Pin 24):. OF (Pin 27):. … |
| File Format / Size | PDF / 257 Kb |
| Document Language | English |
PIN FUNCTIONS. VDD (Pin 23):. CLK (Pin 26):. GND (Pin 24):. OF (Pin 27):. VSS (Pin 25):. GAIN (Pin 28):. FUNCTIONAL BLOCK DIAGRA. W U
Model Line for this Datasheet
Text Version of Document
LTC1420
U U U PIN FUNCTIONS VDD (Pin 23):
Analog 5V Supply. Bypass to GND with a 1µF
CLK (Pin 26):
Conversion Start Signal. This active high ceramic. signal starts a conversion on its rising edge.
GND (Pin 24):
Analog Power Ground.
OF (Pin 27):
Overflow Output. This signal is high when the digital output is 011111111111 or 100000000000.
VSS (Pin 25):
Negative Supply. Can be – 5V or 0V. If VSS is not shorted to GND, bypass to GND with a 1µF ceramic.
GAIN (Pin 28):
Gain Select for Input PGA. 5V selects an input gain of 1, 0V selects a gain of 2.
U U W FUNCTIONAL BLOCK DIAGRA
5V OPTIONAL 3V LOGIC SUPPLY VDD VDD GAIN (PIN 7) (PIN 23) OVDD +AIN S/H PIPELINED 12-BIT ADC OF –AIN D11 (MSB) OUTPUT VCM BUFFERS DIGITAL CORRECTION MODE SELECT LOGIC D0 (LSB) SENSE 2.5V CLK REFERENCE VREF 2.048V 1420 BD V GND GND OGND SS GND (PIN 6) (PIN 8) (PIN 24) 0V OR –5V
W U W TI I G DIAGRA
N + 1 ANALOG N N + 2 INPUT N + 3 tCLOCK tH tL CLK tCONV tACQ DATA N – 3 N – 2 N – 1 N OUTPUT 1420 TD 1420fa 7
U U U PIN FUNCTIONS VDD (Pin 23):
Analog 5V Supply. Bypass to GND with a 1µF
CLK (Pin 26):
Conversion Start Signal. This active high ceramic. signal starts a conversion on its rising edge.
GND (Pin 24):
Analog Power Ground.
OF (Pin 27):
Overflow Output. This signal is high when the digital output is 011111111111 or 100000000000.
VSS (Pin 25):
Negative Supply. Can be – 5V or 0V. If VSS is not shorted to GND, bypass to GND with a 1µF ceramic.
GAIN (Pin 28):
Gain Select for Input PGA. 5V selects an input gain of 1, 0V selects a gain of 2.
U U W FUNCTIONAL BLOCK DIAGRA
5V OPTIONAL 3V LOGIC SUPPLY VDD VDD GAIN (PIN 7) (PIN 23) OVDD +AIN S/H PIPELINED 12-BIT ADC OF –AIN D11 (MSB) OUTPUT VCM BUFFERS DIGITAL CORRECTION MODE SELECT LOGIC D0 (LSB) SENSE 2.5V CLK REFERENCE VREF 2.048V 1420 BD V GND GND OGND SS GND (PIN 6) (PIN 8) (PIN 24) 0V OR –5V
W U W TI I G DIAGRA
N + 1 ANALOG N N + 2 INPUT N + 3 tCLOCK tH tL CLK tCONV tACQ DATA N – 3 N – 2 N – 1 N OUTPUT 1420 TD 1420fa 7
