Datasheet LTC1748 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 14-Bit, 80Msps Low Noise ADC |
| Pages / Page | 20 / 9 — TYPICAL PERFOR A CE CHARACTERISTICS. Offset and Gain Error vs … |
| File Format / Size | PDF / 541 Kb |
| Document Language | English |
TYPICAL PERFOR A CE CHARACTERISTICS. Offset and Gain Error vs Temperature. Supply Current vs Sample Rate. PI FU CTIO S
Model Line for this Datasheet
Text Version of Document
LTC1748
W U TYPICAL PERFOR A CE CHARACTERISTICS Offset and Gain Error vs Temperature Supply Current vs Sample Rate
8 300 TA = 25°C 6 290 GAIN ERROR 4 280 2 270 OFFSET ERROR 0 260 ERROR (LSB) –2 250 SUPPLY CURRENT (mA) –4 240 –6 230 –8 – 50 –30 –10 10 30 50 70 90 0 20 40 60 80 100 TEMPERATURE (°C) SAMPLE RATE (Msps) 1748 G32 1748 G35
U U U PI FU CTIO S SENSE (Pin 1):
Reference Sense Pin. Ground selects ±1V.
MSBINV (Pin 22):
MSB Inversion Control. Low inverts VDD selects ±1.6V. Greater than 1V and less than 1.6V the MSB, 2’s complement output format. High does not applied to the SENSE pin selects an input range of ±VSENSE, invert the MSB, offset binary output format. ±1.6V is the largest valid input range.
ENC (Pin 23):
Encode Input. The input sample starts on the
VCM (Pin 2):
2.35V Output and Input Common Mode Bias. positive edge. Bypass to ground with 4.7µF ceramic chip capacitor.
ENC (Pin 24):
Encode Complement Input. Conversion
GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37):
ADC Power starts on the negative edge. Bypass to ground with 0.1µF Ground. ceramic for single-ended ENCODE signal.
A + IN (Pin 4):
Positive Differential Analog Input.
OE (Pin 25):
Output Enable. Low enables outputs. Logic
A –
high makes outputs Hi-Z. OE should not exceed the
IN (Pin 5):
Negative Differential Analog Input. votlage on OV
V
DD.
DD (Pins 7, 8, 17, 18, 20):
5V Supply. Bypass to AGND with 1µF ceramic chip capacitors at Pin 8 and Pin 18.
CLKOUT (Pin 26):
Data Valid Output. Latch data on the rising edge of CLKOUT.
REFLB (Pin 10):
ADC Low Reference. Bypass to Pin 11 with 0.1µF ceramic chip capacitor. Do not connect to
OGND (Pins 27, 38, 47):
Output Driver Ground. Pin␣ 14.
D0-D3 (Pins 28 to 31):
Digital Outputs.
REFHA (Pin 11):
ADC High Reference. Bypass to Pin 10 with
OVDD (Pins 32, 43):
Positive Supply for the Output Driv- 0.1µF ceramic chip capacitor, to Pin 14 with a 4.7µF ceramic ers. Bypass to ground with 0.1µF ceramic chip capacitor. capacitor and to ground with 1µF ceramic capacitor.
D4-D6 (Pins 33 to 35):
Digital Outputs.
REFLA (Pin 14):
ADC Low Reference. Bypass to Pin 15 with
D7-D10 (Pins 39 to 42):
Digital Outputs. 0.1µF ceramic chip capacitor, to Pin 11 with a 4.7µF ce-
D11-D13 (Pins 44 to 46):
Digital Outputs. ramic capacitor and to ground with 1µF ceramic capacitor.
OF (Pin 48):
Over/Under Flow Output. High when an over
REFHB (Pin 15):
ADC High Reference. Bypass to Pin 14 or under flow has occurred. with 0.1µF ceramic chip capacitor. Do not connect to Pin␣ 11. 1748fa 9
W U TYPICAL PERFOR A CE CHARACTERISTICS Offset and Gain Error vs Temperature Supply Current vs Sample Rate
8 300 TA = 25°C 6 290 GAIN ERROR 4 280 2 270 OFFSET ERROR 0 260 ERROR (LSB) –2 250 SUPPLY CURRENT (mA) –4 240 –6 230 –8 – 50 –30 –10 10 30 50 70 90 0 20 40 60 80 100 TEMPERATURE (°C) SAMPLE RATE (Msps) 1748 G32 1748 G35
U U U PI FU CTIO S SENSE (Pin 1):
Reference Sense Pin. Ground selects ±1V.
MSBINV (Pin 22):
MSB Inversion Control. Low inverts VDD selects ±1.6V. Greater than 1V and less than 1.6V the MSB, 2’s complement output format. High does not applied to the SENSE pin selects an input range of ±VSENSE, invert the MSB, offset binary output format. ±1.6V is the largest valid input range.
ENC (Pin 23):
Encode Input. The input sample starts on the
VCM (Pin 2):
2.35V Output and Input Common Mode Bias. positive edge. Bypass to ground with 4.7µF ceramic chip capacitor.
ENC (Pin 24):
Encode Complement Input. Conversion
GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37):
ADC Power starts on the negative edge. Bypass to ground with 0.1µF Ground. ceramic for single-ended ENCODE signal.
A + IN (Pin 4):
Positive Differential Analog Input.
OE (Pin 25):
Output Enable. Low enables outputs. Logic
A –
high makes outputs Hi-Z. OE should not exceed the
IN (Pin 5):
Negative Differential Analog Input. votlage on OV
V
DD.
DD (Pins 7, 8, 17, 18, 20):
5V Supply. Bypass to AGND with 1µF ceramic chip capacitors at Pin 8 and Pin 18.
CLKOUT (Pin 26):
Data Valid Output. Latch data on the rising edge of CLKOUT.
REFLB (Pin 10):
ADC Low Reference. Bypass to Pin 11 with 0.1µF ceramic chip capacitor. Do not connect to
OGND (Pins 27, 38, 47):
Output Driver Ground. Pin␣ 14.
D0-D3 (Pins 28 to 31):
Digital Outputs.
REFHA (Pin 11):
ADC High Reference. Bypass to Pin 10 with
OVDD (Pins 32, 43):
Positive Supply for the Output Driv- 0.1µF ceramic chip capacitor, to Pin 14 with a 4.7µF ceramic ers. Bypass to ground with 0.1µF ceramic chip capacitor. capacitor and to ground with 1µF ceramic capacitor.
D4-D6 (Pins 33 to 35):
Digital Outputs.
REFLA (Pin 14):
ADC Low Reference. Bypass to Pin 15 with
D7-D10 (Pins 39 to 42):
Digital Outputs. 0.1µF ceramic chip capacitor, to Pin 11 with a 4.7µF ce-
D11-D13 (Pins 44 to 46):
Digital Outputs. ramic capacitor and to ground with 1µF ceramic capacitor.
OF (Pin 48):
Over/Under Flow Output. High when an over
REFHB (Pin 15):
ADC High Reference. Bypass to Pin 14 or under flow has occurred. with 0.1µF ceramic chip capacitor. Do not connect to Pin␣ 11. 1748fa 9
