Datasheet LTC1857, LTC1858, LTC1859 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 8-Channel, 16-Bit, 100ksps SoftSpan A/D Converters with Shutdown |
| Pages / Page | 22 / 8 — PIN FUNCTIONS. DGND (Pin 24):. RD (Pin 27):. SDI (Pin 25):. CONVST (Pin … |
| File Format / Size | PDF / 393 Kb |
| Document Language | English |
PIN FUNCTIONS. DGND (Pin 24):. RD (Pin 27):. SDI (Pin 25):. CONVST (Pin 28):. SCK (Pin 26):. FUNCTIONAL BLOCK DIAGRAM. TEST CIRCUITS
Model Line for this Datasheet
- LTC1857CG#PBF LTC1857CG#PBF LTC1857CG#TRPBF LTC1857CG#TRPBF LTC1857IG#PBF LTC1857IG#PBF LTC1857IG#TRPBF LTC1857IG#TRPBF
Text Version of Document
LTC1857/LTC1858/LTC1859
PIN FUNCTIONS DGND (Pin 24):
Digital Ground.
RD (Pin 27):
Read Input. This active low signal enables
SDI (Pin 25):
Serial Data Input. SDI will ignore clocked the digital output pin SDO. data while RD is high.
CONVST (Pin 28):
Conversion Start. This active high signal
SCK (Pin 26):
Serial Data Clock. starts a conversion on its rising edge.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD MUX ADDRESS AND RANGE CH0 CONVST CH1 CONTROL LOGIC SDI INTERNAL BUSY CLOCK INPUT MUX • AND • RANGE • SELECT SCK + 12-/14-/16-BIT RD CH7 DATA OUT SAMPLING ADC SERIAL I/O COM – OVDD SDO 4.096V 2.5V REFERENCE 1.6384X 8k ADC– MUXOUT+ MUXOUT– ADC+ 1859 BD AGND1 VREF REFCOMP AGND2 AGND3 DGND
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 1k 1k DN DN DN DN 1k 25pF 25pF 1k 25pF 25pF (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL (A) VOH TO Hi-Z (B) VOL TO Hi-Z 1859 TC01 1859 TC02 185789fb 8 For more information www.linear.com/LTC1857 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter and Multplexer Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Test Circuits Timing Diagrams Operation Applications Information Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS DGND (Pin 24):
Digital Ground.
RD (Pin 27):
Read Input. This active low signal enables
SDI (Pin 25):
Serial Data Input. SDI will ignore clocked the digital output pin SDO. data while RD is high.
CONVST (Pin 28):
Conversion Start. This active high signal
SCK (Pin 26):
Serial Data Clock. starts a conversion on its rising edge.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD MUX ADDRESS AND RANGE CH0 CONVST CH1 CONTROL LOGIC SDI INTERNAL BUSY CLOCK INPUT MUX • AND • RANGE • SELECT SCK + 12-/14-/16-BIT RD CH7 DATA OUT SAMPLING ADC SERIAL I/O COM – OVDD SDO 4.096V 2.5V REFERENCE 1.6384X 8k ADC– MUXOUT+ MUXOUT– ADC+ 1859 BD AGND1 VREF REFCOMP AGND2 AGND3 DGND
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 1k 1k DN DN DN DN 1k 25pF 25pF 1k 25pF 25pF (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL (A) VOH TO Hi-Z (B) VOL TO Hi-Z 1859 TC01 1859 TC02 185789fb 8 For more information www.linear.com/LTC1857 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter and Multplexer Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Test Circuits Timing Diagrams Operation Applications Information Package Description Revision History Typical Application Related Parts
