Datasheet LTC1864, LTC1865 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | µPower, 16-Bit, 250ksps 1- and 2-Channel ADCs in MSOP |
| Pages / Page | 24 / 10 — PIN FUNCTIONS. LTC1864. VREF (Pin 1):. SDO (Pin 6):. IN+, IN– (Pins 2, … |
| File Format / Size | PDF / 387 Kb |
| Document Language | English |
PIN FUNCTIONS. LTC1864. VREF (Pin 1):. SDO (Pin 6):. IN+, IN– (Pins 2, 3):. SCK (Pin 7):. GND (Pin 4):. VCC (Pin 8):. CONV (Pin 5):
Model Line for this Datasheet
- LTC1864ACMS8#PBF LTC1864ACMS8#PBF LTC1864ACMS8#TRPBF LTC1864ACMS8#TRPBF LTC1864ACS8#PBF LTC1864ACS8#PBF LTC1864ACS8#TRPBF LTC1864ACS8#TRPBF LTC1864AHMS8#PBF LTC1864AHMS8#PBF LTC1864AHMS8#TRPBF LTC1864AHMS8#TRPBF LTC1864AIMS8#PBF LTC1864AIMS8#PBF LTC1864AIMS8#TRPBF LTC1864AIMS8#TRPBF LTC1864AIS8#PBF LTC1864AIS8#PBF LTC1864AIS8#TRPBF LTC1864AIS8#TRPBF LTC1864CMS8#PBF LTC1864CMS8#PBF LTC1864CMS8#TRPBF LTC1864CMS8#TRPBF LTC1864CS8#PBF LTC1864CS8#PBF LTC1864CS8#TRPBF LTC1864CS8#TRPBF LTC1864HMS8#PBF LTC1864HMS8#PBF LTC1864HMS8#TRPBF LTC1864HMS8#TRPBF LTC1864IMS8#PBF LTC1864IMS8#PBF LTC1864IMS8#TRPBF LTC1864IMS8#TRPBF LTC1864IS8#PBF LTC1864IS8#PBF LTC1864IS8#TRPBF LTC1864IS8#TRPBF
- LTC1865ACMS#PBF LTC1865ACMS#PBF LTC1865ACMS#TRPBF LTC1865ACMS#TRPBF LTC1865ACS8#PBF LTC1865ACS8#PBF LTC1865ACS8#TRPBF LTC1865ACS8#TRPBF LTC1865AHMS#PBF LTC1865AHMS#PBF LTC1865AHMS#TRPBF LTC1865AHMS#TRPBF LTC1865AIMS#PBF LTC1865AIMS#PBF LTC1865AIMS#TRPBF LTC1865AIMS#TRPBF LTC1865AIS8#PBF LTC1865AIS8#PBF LTC1865AIS8#TRPBF LTC1865AIS8#TRPBF LTC1865CMS#PBF LTC1865CMS#PBF LTC1865CMS#TRPBF LTC1865CMS#TRPBF LTC1865CS8#PBF LTC1865CS8#PBF LTC1865CS8#TRPBF LTC1865CS8#TRPBF LTC1865HMS#PBF LTC1865HMS#PBF LTC1865HMS#TRPBF LTC1865HMS#TRPBF LTC1865IMS#PBF LTC1865IMS#PBF LTC1865IMS#TRPBF LTC1865IMS#TRPBF LTC1865IS8#PBF LTC1865IS8#PBF LTC1865IS8#TRPBF LTC1865IS8#TRPBF
Text Version of Document
LTC1864/LTC1865
PIN FUNCTIONS LTC1864 VREF (Pin 1):
Reference Input. The reference input defi nes powers down. A logic low on this input enables the SDO the span of the A/D converter and must be kept free of pin, allowing the data to be shifted out. noise with respect to GND.
SDO (Pin 6):
Digital Data Output. The A/D conversion
IN+, IN– (Pins 2, 3):
Analog Inputs. These inputs must result is shifted out of this pin. be free of noise with respect to GND.
SCK (Pin 7):
Shift Clock Input. This clock synchronizes
GND (Pin 4):
Analog Ground. GND should be tied directly the serial data transfer. to an analog ground plane.
VCC (Pin 8):
Positive Supply. This supply must be kept
CONV (Pin 5):
Convert Input. A logic high on this input free of noise and ripple by bypassing directly to the starts the A/D conversion process. If the CONV input is analog ground plane. left high after the A/D conversion is fi nished, the part
LTC1865 (MSOP Package) CONV (Pin 1):
Convert Input. A logic high on this input
SDO (Pin 7):
Digital Data Output. The A/D conversion starts the A/D conversion process. If the CONV input is result is shifted out of this output. left high after the A/D conversion is fi nished, the part
SCK (Pin 8):
Shift Clock Input. This clock synchronizes powers down. A logic low on this input enables the SDO the serial data transfer. pin, allowing the data to be shifted out.
V CH0, CH1 (Pins 2, 3):
Analog Inputs. These inputs must
CC (Pin 9):
Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the be free of noise with respect to AGND. analog ground plane.
AGND (Pin 4):
Analog Ground. AGND should be tied directly
V
to an analog ground plane.
REF (Pin 10):
Reference Input. The reference input defi nes the span of the A/D converter and must be kept free of
DGND (Pin 5):
Digital Ground. DGND should be tied directly noise with respect to AGND. to an analog ground plane.
SDI (Pin 6):
Digital Data Input. The A/D confi guration word is shifted into this input.
LTC1865 (SO-8 Package) CONV (Pin 1):
Convert Input. A logic high on this input
SDI (Pin 5):
Digital Data Input. The A/D confi guration starts the A/D conversion process. If the CONV input is word is shifted into this input. left high after the A/D conversion is fi nished, the part
SDO (Pin 6):
Digital Data Output. The A/D conversion powers down. A logic low on this input enables the SDO result is shifted out of this output. pin, allowing the data to be shifted out.
SCK (Pin 7):
Shift Clock Input. This clock synchronizes
CH0, CH1 (Pins 2, 3):
Analog Inputs. These inputs must the serial data transfer. be free of noise with respect to GND.
V GND (Pin 4):
Analog Ground. GND should be tied directly
CC (Pin 8):
Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog to an analog ground plane. ground plane. VREF is tied internally to this pin. 18645fb 10
PIN FUNCTIONS LTC1864 VREF (Pin 1):
Reference Input. The reference input defi nes powers down. A logic low on this input enables the SDO the span of the A/D converter and must be kept free of pin, allowing the data to be shifted out. noise with respect to GND.
SDO (Pin 6):
Digital Data Output. The A/D conversion
IN+, IN– (Pins 2, 3):
Analog Inputs. These inputs must result is shifted out of this pin. be free of noise with respect to GND.
SCK (Pin 7):
Shift Clock Input. This clock synchronizes
GND (Pin 4):
Analog Ground. GND should be tied directly the serial data transfer. to an analog ground plane.
VCC (Pin 8):
Positive Supply. This supply must be kept
CONV (Pin 5):
Convert Input. A logic high on this input free of noise and ripple by bypassing directly to the starts the A/D conversion process. If the CONV input is analog ground plane. left high after the A/D conversion is fi nished, the part
LTC1865 (MSOP Package) CONV (Pin 1):
Convert Input. A logic high on this input
SDO (Pin 7):
Digital Data Output. The A/D conversion starts the A/D conversion process. If the CONV input is result is shifted out of this output. left high after the A/D conversion is fi nished, the part
SCK (Pin 8):
Shift Clock Input. This clock synchronizes powers down. A logic low on this input enables the SDO the serial data transfer. pin, allowing the data to be shifted out.
V CH0, CH1 (Pins 2, 3):
Analog Inputs. These inputs must
CC (Pin 9):
Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the be free of noise with respect to AGND. analog ground plane.
AGND (Pin 4):
Analog Ground. AGND should be tied directly
V
to an analog ground plane.
REF (Pin 10):
Reference Input. The reference input defi nes the span of the A/D converter and must be kept free of
DGND (Pin 5):
Digital Ground. DGND should be tied directly noise with respect to AGND. to an analog ground plane.
SDI (Pin 6):
Digital Data Input. The A/D confi guration word is shifted into this input.
LTC1865 (SO-8 Package) CONV (Pin 1):
Convert Input. A logic high on this input
SDI (Pin 5):
Digital Data Input. The A/D confi guration starts the A/D conversion process. If the CONV input is word is shifted into this input. left high after the A/D conversion is fi nished, the part
SDO (Pin 6):
Digital Data Output. The A/D conversion powers down. A logic low on this input enables the SDO result is shifted out of this output. pin, allowing the data to be shifted out.
SCK (Pin 7):
Shift Clock Input. This clock synchronizes
CH0, CH1 (Pins 2, 3):
Analog Inputs. These inputs must the serial data transfer. be free of noise with respect to GND.
V GND (Pin 4):
Analog Ground. GND should be tied directly
CC (Pin 8):
Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog to an analog ground plane. ground plane. VREF is tied internally to this pin. 18645fb 10
