Datasheet LTC1864L, LTC1865L (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | µPower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP |
| Pages / Page | 16 / 4 — RECO E DED OPERATI G CO DITIO S The. denotes specifications which apply … |
| File Format / Size | PDF / 366 Kb |
| Document Language | English |
RECO E DED OPERATI G CO DITIO S The. denotes specifications which apply over the
Model Line for this Datasheet
- LTC1864LACMS8#PBF LTC1864LACMS8#PBF LTC1864LACMS8#TRPBF LTC1864LACMS8#TRPBF LTC1864LACS8#PBF LTC1864LACS8#PBF LTC1864LACS8#TRPBF LTC1864LACS8#TRPBF LTC1864LAIMS8#PBF LTC1864LAIMS8#PBF LTC1864LAIMS8#TRPBF LTC1864LAIMS8#TRPBF LTC1864LAIS8#PBF LTC1864LAIS8#PBF LTC1864LAIS8#TRPBF LTC1864LAIS8#TRPBF LTC1864LCMS8#PBF LTC1864LCMS8#PBF LTC1864LCMS8#TRPBF LTC1864LCMS8#TRPBF LTC1864LCS8#PBF LTC1864LCS8#PBF LTC1864LCS8#TRPBF LTC1864LCS8#TRPBF LTC1864LIMS8#PBF LTC1864LIMS8#PBF LTC1864LIMS8#TRPBF LTC1864LIMS8#TRPBF LTC1864LIS8#PBF LTC1864LIS8#PBF LTC1864LIS8#TRPBF LTC1864LIS8#TRPBF
- LTC1865LACMS#PBF LTC1865LACMS#PBF LTC1865LACMS#TRPBF LTC1865LACMS#TRPBF LTC1865LACS8#PBF LTC1865LACS8#PBF LTC1865LACS8#TRPBF LTC1865LACS8#TRPBF LTC1865LAIMS#PBF LTC1865LAIMS#PBF LTC1865LAIMS#TRPBF LTC1865LAIMS#TRPBF LTC1865LAIS8#PBF LTC1865LAIS8#PBF LTC1865LAIS8#TRPBF LTC1865LAIS8#TRPBF LTC1865LCMS#PBF LTC1865LCMS#PBF LTC1865LCMS#TRPBF LTC1865LCMS#TRPBF LTC1865LCS8#PBF LTC1865LCS8#PBF LTC1865LCS8#TRPBF LTC1865LCS8#TRPBF LTC1865LIMS#PBF LTC1865LIMS#PBF LTC1865LIMS#TRPBF LTC1865LIMS#TRPBF LTC1865LIS8#PBF LTC1865LIS8#PBF LTC1865LIS8#TRPBF LTC1865LIS8#TRPBF
Text Version of Document
LTC1864L/LTC1865L
WW U U U U RECO E DED OPERATI G CO DITIO S The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25
°
C. LTC1864L/LTC1865L SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage 2.7 3.6 V fSCK Clock Frequency ● DC 8 MHz tCYC Total Cycle Time 16 • SCK + tCONV µs tSMPL Analog Input Sampling Time (Note 5) LTC1864L 16 SCK LTC1865L 14 SCK tsuCONV Setup Time CONV↓ Before First SCK↑ 60 ns (See Figure 1) thDI Hold Time SDI After SCK↑ LTC1865L 30 ns tsuDI Setup Time SDI Stable Before SCK↑ LTC1865L 30 ns tWHCLK SCK High Time fSCK = fSCK(MAX) 45% 1/fSCK tWLCLK SCK Low Time fSCK = fSCK(MAX) 45% 1/fSCK tWHCONV CONV High Time Between Data tCONV µs Transfer Cycles tWLCONV CONV Low Time During Data Transfer 16 SCK thCONV Hold Time CONV Low After Last SCK↑ 26 ns
W U TI I G CHARACTERISTICS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25
°
C. VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. LTC1864L/LTC1865L SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tCONV Conversion Time (See Figure 1) ● 3.7 4.66 µs fSMPL(MAX) Maximum Sampling Frequency ● 150 kHz tdDO Delay Time, SCK↓ to SDO Data Valid CLOAD = 20pF 45 55 ns ● 60 ns tdis Delay Time, CONV↑ to SDO Hi-Z ● 55 120 ns ten Delay Time, CONV↓ to SDO Enabled CLOAD = 20pF ● 35 120 ns thDO Time Output Data Remains CLOAD = 20pF ● 5 15 ns Valid After SCK↓ tr SDO Rise Time CLOAD = 20pF 25 ns tf SDO Fall Time CLOAD = 20pF 12 ns
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 4:
Channel leakage current is measured while the part is in sample of a device may be impaired. mode.
Note 2:
All voltage values are with respect to GND.
Note 5:
Assumes fSCK = fSCK(MAX) In the case of the LTC1864L SCK does
Note 3:
Integral nonlinearity is defined as deviation of a code from a not have to be clocked during this time if the SDO data word is not straight line passing through the actual endpoints of the transfer curve. desired. In the case of the LTC1865L a minimum of 2 clocks are required The deviation is measured from the center of the quantization band. on the SCK input after CONV falls to configure the MUX during this time. sn18645L 18645Lfs 4
WW U U U U RECO E DED OPERATI G CO DITIO S The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25
°
C. LTC1864L/LTC1865L SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage 2.7 3.6 V fSCK Clock Frequency ● DC 8 MHz tCYC Total Cycle Time 16 • SCK + tCONV µs tSMPL Analog Input Sampling Time (Note 5) LTC1864L 16 SCK LTC1865L 14 SCK tsuCONV Setup Time CONV↓ Before First SCK↑ 60 ns (See Figure 1) thDI Hold Time SDI After SCK↑ LTC1865L 30 ns tsuDI Setup Time SDI Stable Before SCK↑ LTC1865L 30 ns tWHCLK SCK High Time fSCK = fSCK(MAX) 45% 1/fSCK tWLCLK SCK Low Time fSCK = fSCK(MAX) 45% 1/fSCK tWHCONV CONV High Time Between Data tCONV µs Transfer Cycles tWLCONV CONV Low Time During Data Transfer 16 SCK thCONV Hold Time CONV Low After Last SCK↑ 26 ns
W U TI I G CHARACTERISTICS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25
°
C. VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. LTC1864L/LTC1865L SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tCONV Conversion Time (See Figure 1) ● 3.7 4.66 µs fSMPL(MAX) Maximum Sampling Frequency ● 150 kHz tdDO Delay Time, SCK↓ to SDO Data Valid CLOAD = 20pF 45 55 ns ● 60 ns tdis Delay Time, CONV↑ to SDO Hi-Z ● 55 120 ns ten Delay Time, CONV↓ to SDO Enabled CLOAD = 20pF ● 35 120 ns thDO Time Output Data Remains CLOAD = 20pF ● 5 15 ns Valid After SCK↓ tr SDO Rise Time CLOAD = 20pF 25 ns tf SDO Fall Time CLOAD = 20pF 12 ns
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 4:
Channel leakage current is measured while the part is in sample of a device may be impaired. mode.
Note 2:
All voltage values are with respect to GND.
Note 5:
Assumes fSCK = fSCK(MAX) In the case of the LTC1864L SCK does
Note 3:
Integral nonlinearity is defined as deviation of a code from a not have to be clocked during this time if the SDO data word is not straight line passing through the actual endpoints of the transfer curve. desired. In the case of the LTC1865L a minimum of 2 clocks are required The deviation is measured from the center of the quantization band. on the SCK input after CONV falls to configure the MUX during this time. sn18645L 18645Lfs 4
