Datasheet LTC2145-12, LTC2144-12, LTC2143-12 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 12-Bit, 125Msps Low Power Dual ADCs |
| Pages / Page | 38 / 7 — POWER REQUIREMENTS. The. denotes the specifications which apply over the … |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
POWER REQUIREMENTS. The. denotes the specifications which apply over the full operating temperature
Model Line for this Datasheet
- LTC2143CUP-12#PBF LTC2143CUP-12#PBF LTC2143CUP-12#TRPBF LTC2143CUP-12#TRPBF LTC2143IUP-12#PBF LTC2143IUP-12#PBF LTC2143IUP-12#TRPBF LTC2143IUP-12#TRPBF
Text Version of Document
LTC2145-12/ LTC2144-12/LTC2143-12
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2145-12 LTC2144-12 LTC2143-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS CMOS Output Modes: Full Data Rate and Double Data Rate
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9 V IVDD Analog Supply Current DC Input l 101.5 112 79.8 89 60.4 68 mA Sine Wave Input 102.2 80.3 60.9 mA IOVDD Digital Supply Current Sine Wave Input, OVDD = 1.2V 7.3 6.2 4.7 mA PDISS Power Dissipation DC Input l 183 202 144 161 109 123 mW Sine Wave Input, OVDD = 1.2V 193 152 115 mW
LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Input, 1.75mA Mode 103.4 81.6 62.1 mA Sine Input, 3.5mA Mode l 104.6 119 82.8 94 63.4 73 mA IOVDD Digital Supply Current Sine Input, 1.75mA Mode 30.6 30.3 30.1 mA (0VDD = 1.8V) Sine Input, 3.5mA Mode l 57.9 69 57.6 68 57.3 68 mA PDISS Power Dissipation Sine Input, 1.75mA Mode 241 201 166 mW Sine Input, 3.5mA Mode l 293 339 253 292 217 254 mW
All Output Modes
PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 16 16 16 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 20 20 mW (No increase for Nap or Sleep Modes)
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2145-12 LTC2144-12 LTC2143-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 1 125 1 105 1 80 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 500 4.52 4.76 500 5.93 6.25 500 ns Duty Cycle Stabilizer On l 2 4 500 2 4.76 500 2 6.25 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 500 4.52 4.76 500 5.93 6.25 500 ns Duty Cycle Stabilizer On l 2 4 500 2 4.76 500 2 6.25 500 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode 6 Cycles Double Data Rate Mode 6.5 Cycles 21454312fa 7
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2145-12 LTC2144-12 LTC2143-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS CMOS Output Modes: Full Data Rate and Double Data Rate
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9 V IVDD Analog Supply Current DC Input l 101.5 112 79.8 89 60.4 68 mA Sine Wave Input 102.2 80.3 60.9 mA IOVDD Digital Supply Current Sine Wave Input, OVDD = 1.2V 7.3 6.2 4.7 mA PDISS Power Dissipation DC Input l 183 202 144 161 109 123 mW Sine Wave Input, OVDD = 1.2V 193 152 115 mW
LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Input, 1.75mA Mode 103.4 81.6 62.1 mA Sine Input, 3.5mA Mode l 104.6 119 82.8 94 63.4 73 mA IOVDD Digital Supply Current Sine Input, 1.75mA Mode 30.6 30.3 30.1 mA (0VDD = 1.8V) Sine Input, 3.5mA Mode l 57.9 69 57.6 68 57.3 68 mA PDISS Power Dissipation Sine Input, 1.75mA Mode 241 201 166 mW Sine Input, 3.5mA Mode l 293 339 253 292 217 254 mW
All Output Modes
PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 16 16 16 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 20 20 mW (No increase for Nap or Sleep Modes)
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2145-12 LTC2144-12 LTC2143-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 1 125 1 105 1 80 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 500 4.52 4.76 500 5.93 6.25 500 ns Duty Cycle Stabilizer On l 2 4 500 2 4.76 500 2 6.25 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 500 4.52 4.76 500 5.93 6.25 500 ns Duty Cycle Stabilizer On l 2 4 500 2 4.76 500 2 6.25 500 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode 6 Cycles Double Data Rate Mode 6.5 Cycles 21454312fa 7
