Datasheet LTC2145-14, LTC2144-14, LTC2143-14 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | 14-Bit, 125Msps Low Power Dual ADCs |
| Pages / Page | 38 / 1 — FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. 64k Point … |
| File Format / Size | PDF / 668 Kb |
| Document Language | English |
FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. 64k Point 2-Tone FFT, fIN = 69MHz,. 70MHz, –1dBFS, 125Msps
Model Line for this Datasheet
- LTC2143CUP-14#PBF LTC2143CUP-14#PBF LTC2143CUP-14#TRPBF LTC2143CUP-14#TRPBF LTC2143IUP-14#PBF LTC2143IUP-14#PBF LTC2143IUP-14#TRPBF LTC2143IUP-14#TRPBF
Text Version of Document
LTC2145-14/ LTC2144-14/LTC2143-14 14-Bit, 125Msps/105Msps/ 80Msps Low Power Dual ADCs
FEATURES DESCRIPTION
n Two-Channel Simultaneously Sampling ADC The LTC®2145-14/LTC2144-14/LTC2143-14 are 2-channel n 73.1dB SNR simultaneous sampling 14-bit A/D converters designed n 90dB SFDR for digitizing high frequency, wide dynamic range signals. n Low Power: 189mW/149mW/113mW Total They are perfect for demanding communications applica- 95mW/75mW/57mW per Channel tions with AC performance that includes 73.1dB SNR and n Single 1.8V Supply 90dB spurious free dynamic range (SFDR). Ultralow jitter n CMOS, DDR CMOS, or DDR LVDS Outputs of 0.08psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 750MHz Full Power Bandwidth S/H DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) n Optional Data Output Randomizer and no missing codes over temperature. The transition n Optional Clock Duty Cycle Stabilizer noise is 1.2LSB n Shutdown and Nap Modes RMS. n Serial SPI Port for Configuration The digital outputs can be either full rate CMOS, double n 64-Pin (9mm × 9mm) QFN Package data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to
APPLICATIONS
range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differentially n Communications or single-ended with a sine wave, PECL, LVDS, TTL, or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Software Defined Radios lows high performance at full speed for a wide range of n Portable Medical Imaging clock duty cycles. n Multi-Channel Data Acquisition L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Nondestructive Testing Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION 64k Point 2-Tone FFT, fIN = 69MHz,
1.8V 1.8V
70MHz, –1dBFS, 125Msps
VDD OVDD 0 –10 CH 1 –20 14-BIT D1_13 ANALOG S/H ADC CORE t –30 INPUT t t –40 CMOS, D1_0 DDR CMOS –50 OR DDR LVDS D2_13 –60 OUTPUTS OUTPUT t –70 CH 2 t DRIVERS 14-BIT t ANALOG S/H AMPLITUDE (dBFS) –80 ADC CORE D2_0 INPUT –90 –100 –110 125MHz CLOCK –120 0 10 20 30 40 50 60 CONTROL CLOCK FREQUENCY (MHz) 21454314 TA03b 21454314 TA01a GND OGND 21454314fa 1
FEATURES DESCRIPTION
n Two-Channel Simultaneously Sampling ADC The LTC®2145-14/LTC2144-14/LTC2143-14 are 2-channel n 73.1dB SNR simultaneous sampling 14-bit A/D converters designed n 90dB SFDR for digitizing high frequency, wide dynamic range signals. n Low Power: 189mW/149mW/113mW Total They are perfect for demanding communications applica- 95mW/75mW/57mW per Channel tions with AC performance that includes 73.1dB SNR and n Single 1.8V Supply 90dB spurious free dynamic range (SFDR). Ultralow jitter n CMOS, DDR CMOS, or DDR LVDS Outputs of 0.08psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 750MHz Full Power Bandwidth S/H DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) n Optional Data Output Randomizer and no missing codes over temperature. The transition n Optional Clock Duty Cycle Stabilizer noise is 1.2LSB n Shutdown and Nap Modes RMS. n Serial SPI Port for Configuration The digital outputs can be either full rate CMOS, double n 64-Pin (9mm × 9mm) QFN Package data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to
APPLICATIONS
range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differentially n Communications or single-ended with a sine wave, PECL, LVDS, TTL, or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Software Defined Radios lows high performance at full speed for a wide range of n Portable Medical Imaging clock duty cycles. n Multi-Channel Data Acquisition L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Nondestructive Testing Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION 64k Point 2-Tone FFT, fIN = 69MHz,
1.8V 1.8V
70MHz, –1dBFS, 125Msps
VDD OVDD 0 –10 CH 1 –20 14-BIT D1_13 ANALOG S/H ADC CORE t –30 INPUT t t –40 CMOS, D1_0 DDR CMOS –50 OR DDR LVDS D2_13 –60 OUTPUTS OUTPUT t –70 CH 2 t DRIVERS 14-BIT t ANALOG S/H AMPLITUDE (dBFS) –80 ADC CORE D2_0 INPUT –90 –100 –110 125MHz CLOCK –120 0 10 20 30 40 50 60 CONTROL CLOCK FREQUENCY (MHz) 21454314 TA03b 21454314 TA01a GND OGND 21454314fa 1
