Datasheet LTC2152-12, LTC2151-12, LTC2150-12 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | Single 12-Bit 250Msps ADCs |
| Pages / Page | 30 / 1 — FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. LTC2152-12: 32K … |
| File Format / Size | PDF / 689 Kb |
| Document Language | English |
FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. LTC2152-12: 32K Point 2-Tone FFT,. fIN = 71MHz and 69MHz, 250Msps
Model Line for this Datasheet
- LTC2150CUJ-12#PBF LTC2150CUJ-12#PBF LTC2150CUJ-12#TRPBF LTC2150CUJ-12#TRPBF LTC2150IUJ-12#PBF LTC2150IUJ-12#PBF LTC2150IUJ-12#TRPBF LTC2150IUJ-12#TRPBF
Text Version of Document
LTC2152-12/ LTC2151-12/LTC2150-12 Single 12-Bit 250Msps/ 210Msps/170Msps ADCs
FEATURES DESCRIPTION
n 68.5dB SNR The LTC®2152-12/LTC2151-12/LTC2150-12 are a family n 90dB SFDR of 250Msps/210Msps/170Msps 12-bit A/D converters n Low Power: 347mW/333mW/306mW Total designed for digitizing high frequency, wide dynamic range n Single 1.8V Supply signals. They are perfect for demanding communications n DDR LVDS Outputs applications with AC performance that includes 68.5dB n Easy-to-Drive 1.5VP-P Input Range SNR and 90dB spurious free dynamic range (SFDR). The n 1.25GHz Full Power Bandwidth S/H 1.25GHz input bandwidth allows the ADC to undersample high input frequencies with good performance. The latency n Optional Clock Duty Cycle Stabilizer is only six clock cycles. n Low Power Sleep and Nap Modes n Serial SPI Port for Configuration DC specs include ±0.26LSB INL (typ), ±0.16LSB DNL (typ) n Pin-Compatible 14-Bit Versions and no missing codes over temperature. The transition n 40-Lead (6mm × 6mm) QFN Package noise is 0.54LSBRMS.
APPLICATIONS
The digital outputs are double-data rate (DDR) LVDS. n Communications The ENC+ and ENC– inputs can be driven differentially with n Cellular Basestations a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional n Software Defined Radios clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. n Medical Imaging n High Definition Video L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Testing and Measurement Instruments
TYPICAL APPLICATION LTC2152-12: 32K Point 2-Tone FFT,
VDD
fIN = 71MHz and 69MHz, 250Msps
OVDD 0 D10_11 –20 12-BIT ANALOG CORRECTION • S/H OUTPUT PIPELINED DDR INPUT LOGIC DRIVERS • ADC • LVDS –40 D0_1 –60 CLOCK/DUTY OGND CLOCK CYCLE AMPLITUDE (dBFS) –80 CONTROL –100 21521012 TA01a –120 GND 0 20 40 60 80 100 120 FREQUENCY (MHz) 21521012 TA01b 21521012fa For more information www.linear.com/LTC2152-12 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Typical Applications Package Description Typical Application Related Parts
FEATURES DESCRIPTION
n 68.5dB SNR The LTC®2152-12/LTC2151-12/LTC2150-12 are a family n 90dB SFDR of 250Msps/210Msps/170Msps 12-bit A/D converters n Low Power: 347mW/333mW/306mW Total designed for digitizing high frequency, wide dynamic range n Single 1.8V Supply signals. They are perfect for demanding communications n DDR LVDS Outputs applications with AC performance that includes 68.5dB n Easy-to-Drive 1.5VP-P Input Range SNR and 90dB spurious free dynamic range (SFDR). The n 1.25GHz Full Power Bandwidth S/H 1.25GHz input bandwidth allows the ADC to undersample high input frequencies with good performance. The latency n Optional Clock Duty Cycle Stabilizer is only six clock cycles. n Low Power Sleep and Nap Modes n Serial SPI Port for Configuration DC specs include ±0.26LSB INL (typ), ±0.16LSB DNL (typ) n Pin-Compatible 14-Bit Versions and no missing codes over temperature. The transition n 40-Lead (6mm × 6mm) QFN Package noise is 0.54LSBRMS.
APPLICATIONS
The digital outputs are double-data rate (DDR) LVDS. n Communications The ENC+ and ENC– inputs can be driven differentially with n Cellular Basestations a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional n Software Defined Radios clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. n Medical Imaging n High Definition Video L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Testing and Measurement Instruments
TYPICAL APPLICATION LTC2152-12: 32K Point 2-Tone FFT,
VDD
fIN = 71MHz and 69MHz, 250Msps
OVDD 0 D10_11 –20 12-BIT ANALOG CORRECTION • S/H OUTPUT PIPELINED DDR INPUT LOGIC DRIVERS • ADC • LVDS –40 D0_1 –60 CLOCK/DUTY OGND CLOCK CYCLE AMPLITUDE (dBFS) –80 CONTROL –100 21521012 TA01a –120 GND 0 20 40 60 80 100 120 FREQUENCY (MHz) 21521012 TA01b 21521012fa For more information www.linear.com/LTC2152-12 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Typical Applications Package Description Typical Application Related Parts
