Datasheet LTC2152-14, LTC2151-14, LTC2150-14 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | Single 14-Bit 250Msps ADCs |
| Pages / Page | 32 / 1 — FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. LTC2152-14: 32K … |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. LTC2152-14: 32K Point FFT,. fIN = 15MHz, –1dBFS, 250Msps
Model Line for this Datasheet
- LTC2150CUJ-14#PBF LTC2150CUJ-14#PBF LTC2150CUJ-14#TRPBF LTC2150CUJ-14#TRPBF LTC2150IUJ-14#PBF LTC2150IUJ-14#PBF LTC2150IUJ-14#TRPBF LTC2150IUJ-14#TRPBF
Text Version of Document
LTC2152-14/ LTC2151-14/LTC2150-14 14-Bit 250Msps/ 210Msps/170Msps ADCs
FEATURES DESCRIPTION
n 70dB SNR The LTC®2152-14/LTC2151-14/LTC2150-14 are 250Msps/ n 90dB SFDR 210Msps/170Msps 14-bit A/D converters designed for n Low Power: 356mW/338mW/313mW Total digitizing high frequency, wide dynamic range signals. n Single 1.8V Supply They are perfect for demanding communications applica- n DDR LVDS Outputs tions with AC performance that includes 70dB SNR and n Easy-to-Drive 1.5VP-P Input Range 90dB spurious free dynamic range (SFDR). The 1.25GHz n 1.25GHz Full Power Bandwidth S/H input bandwidth allows the ADC to undersample high n Optional Clock Duty Cycle Stabilizer frequencies with good performance. The latency is only six clock cycles. n Low Power Sleep and Nap Modes n Serial SPI Port for Configuration DC specs include ±0.85LSB INL (typ), ±0.25LSB DNL (typ) n Pin Compatible 12-Bit Versions and no missing codes over temperature. The transition n 40-Pin (6mm × 6mm) QFN Package noise is 1.82LSBRMS.
APPLICATIONS
The digital outputs are double-data rate (DDR) LVDS. n Communications The ENC+ and ENC– inputs can be driven differentially with n Cellular Basestations a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional n Software Defined Radios clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. n Medical Imaging n High Definition Video L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Testing and Measurement Instruments
TYPICAL APPLICATION LTC2152-14: 32K Point FFT, fIN = 15MHz, –1dBFS, 250Msps
VDD 0 OVDD –20 D12_13 14-BIT ANALOG CORRECTION • S/H OUTPUT PIPELINED DDR INPUT LOGIC DRIVERS • –40 ADC • LVDS D0_1 –60 CLOCK/DUTY OGND AMPLITUDE (dBFS) –80 CLOCK CYCLE CONTROL –100 21521014 TA01a –120 0 20 40 60 80 100 120 FREQUENCY (MHz) 21521014 TA01b 21521014fa For more information www.linear.com/LTC2152-14 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Typical Applications Package Description Typical Application Related Parts
FEATURES DESCRIPTION
n 70dB SNR The LTC®2152-14/LTC2151-14/LTC2150-14 are 250Msps/ n 90dB SFDR 210Msps/170Msps 14-bit A/D converters designed for n Low Power: 356mW/338mW/313mW Total digitizing high frequency, wide dynamic range signals. n Single 1.8V Supply They are perfect for demanding communications applica- n DDR LVDS Outputs tions with AC performance that includes 70dB SNR and n Easy-to-Drive 1.5VP-P Input Range 90dB spurious free dynamic range (SFDR). The 1.25GHz n 1.25GHz Full Power Bandwidth S/H input bandwidth allows the ADC to undersample high n Optional Clock Duty Cycle Stabilizer frequencies with good performance. The latency is only six clock cycles. n Low Power Sleep and Nap Modes n Serial SPI Port for Configuration DC specs include ±0.85LSB INL (typ), ±0.25LSB DNL (typ) n Pin Compatible 12-Bit Versions and no missing codes over temperature. The transition n 40-Pin (6mm × 6mm) QFN Package noise is 1.82LSBRMS.
APPLICATIONS
The digital outputs are double-data rate (DDR) LVDS. n Communications The ENC+ and ENC– inputs can be driven differentially with n Cellular Basestations a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional n Software Defined Radios clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. n Medical Imaging n High Definition Video L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Testing and Measurement Instruments
TYPICAL APPLICATION LTC2152-14: 32K Point FFT, fIN = 15MHz, –1dBFS, 250Msps
VDD 0 OVDD –20 D12_13 14-BIT ANALOG CORRECTION • S/H OUTPUT PIPELINED DDR INPUT LOGIC DRIVERS • –40 ADC • LVDS D0_1 –60 CLOCK/DUTY OGND AMPLITUDE (dBFS) –80 CLOCK CYCLE CONTROL –100 21521014 TA01a –120 0 20 40 60 80 100 120 FREQUENCY (MHz) 21521014 TA01b 21521014fa For more information www.linear.com/LTC2152-14 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Typical Applications Package Description Typical Application Related Parts
