Datasheet LTC2158-12 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | Dual 12-Bit 310Msps ADC |
| Pages / Page | 28 / 1 — FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. LTC2158-12 32K … |
| File Format / Size | PDF / 1.5 Mb |
| Document Language | English |
FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. LTC2158-12 32K Point 2-Tone FFT,. fIN = 71MHz and 69MHz, 310Msps
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LTC2158-12 Dual 12-Bit 310Msps ADC
FEATURES DESCRIPTION
n 67.6dBFS SNR The LTC®2158-12 is a 2-channel simultaneous sampling n 88dB SFDR 310Msps 12-bit A/D converter designed for digitizing high n Low Power: 688mW Total frequency, wide dynamic range signals. It is perfect for n Single 1.8V Supply demanding communications applications with AC per- n DDR LVDS Outputs formance that includes 67.6dB SNR and 88dB spurious n 1.32VP-P Input Range free dynamic range (SFDR). The 1.25GHz input bandwidth n 1.25GHz Full Power Bandwidth S/H allows the ADC to undersample high frequencies with n Optional Clock Duty Cycle Stabilizer good performance. The latency is only six clock cycles. n Low Power Sleep and Nap Modes DC specs include ±0.6LSB INL (typ), ±0.1LSB DNL (typ) n Serial SPI Port for Configuration and no missing codes over temperature. The transition n Pin-Compatible 14-Bit Versions noise is 0.6LSBRMS. n 64-Lead (9mm × 9mm) QFN Package The digital outputs are double data rate (DDR) LVDS.
APPLICATIONS
The ENC+ and ENC– inputs can be driven differentially with n Communications a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional n Cellular Basestations clock duty cycle stabilizer allows high performance at full n Software Defined Radios speed for a wide range of clock duty cycles. n Medical Imaging L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n High Definition Video Technology Corporation. All other trademarks are the property of their respective owners. n Testing and Measurement Instruments
TYPICAL APPLICATION LTC2158-12 32K Point 2-Tone FFT,
VDD
fIN = 71MHz and 69MHz, 310Msps
OVDD CHANNEL A 0 DA10_11 12-BIT ANALOG CORRECTION • –20 S/H OUTPUT PIPELINED DDR INPUT LOGIC DRIVERS • ADC CORE LVDS • DA0_1 –40 –60 CLOCK/DUTY OGND CLOCK CYCLE CONTROL AMPLITUDE (dBFS) –80 OV CHANNEL B DD –100 DB10_11 12-BIT • ANALOG CORRECTION –120 S/H OUTPUT PIPELINED • DDR INPUT LOGIC DRIVERS 0 20 40 60 80 100 120 140 ADC CORE • LVDS FREQUENCY (MHz) DB0_1 215812 TA10b GND 215812 TA01 OGND 215812fa For more information www.linear.com/LTC2158-12 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Typical Applications Package Description Related Parts
FEATURES DESCRIPTION
n 67.6dBFS SNR The LTC®2158-12 is a 2-channel simultaneous sampling n 88dB SFDR 310Msps 12-bit A/D converter designed for digitizing high n Low Power: 688mW Total frequency, wide dynamic range signals. It is perfect for n Single 1.8V Supply demanding communications applications with AC per- n DDR LVDS Outputs formance that includes 67.6dB SNR and 88dB spurious n 1.32VP-P Input Range free dynamic range (SFDR). The 1.25GHz input bandwidth n 1.25GHz Full Power Bandwidth S/H allows the ADC to undersample high frequencies with n Optional Clock Duty Cycle Stabilizer good performance. The latency is only six clock cycles. n Low Power Sleep and Nap Modes DC specs include ±0.6LSB INL (typ), ±0.1LSB DNL (typ) n Serial SPI Port for Configuration and no missing codes over temperature. The transition n Pin-Compatible 14-Bit Versions noise is 0.6LSBRMS. n 64-Lead (9mm × 9mm) QFN Package The digital outputs are double data rate (DDR) LVDS.
APPLICATIONS
The ENC+ and ENC– inputs can be driven differentially with n Communications a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional n Cellular Basestations clock duty cycle stabilizer allows high performance at full n Software Defined Radios speed for a wide range of clock duty cycles. n Medical Imaging L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n High Definition Video Technology Corporation. All other trademarks are the property of their respective owners. n Testing and Measurement Instruments
TYPICAL APPLICATION LTC2158-12 32K Point 2-Tone FFT,
VDD
fIN = 71MHz and 69MHz, 310Msps
OVDD CHANNEL A 0 DA10_11 12-BIT ANALOG CORRECTION • –20 S/H OUTPUT PIPELINED DDR INPUT LOGIC DRIVERS • ADC CORE LVDS • DA0_1 –40 –60 CLOCK/DUTY OGND CLOCK CYCLE CONTROL AMPLITUDE (dBFS) –80 OV CHANNEL B DD –100 DB10_11 12-BIT • ANALOG CORRECTION –120 S/H OUTPUT PIPELINED • DDR INPUT LOGIC DRIVERS 0 20 40 60 80 100 120 140 ADC CORE • LVDS FREQUENCY (MHz) DB0_1 215812 TA10b GND 215812 TA01 OGND 215812fa For more information www.linear.com/LTC2158-12 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Typical Applications Package Description Related Parts
