Datasheet LTC2158-14 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Dual 14-Bit 310Msps ADC |
| Pages / Page | 28 / 9 — PIN FUNCTIONS SDI (Pin 60):. LVDS Outputs. OF–/OF+ (Pins 22/23):. SCK … |
| File Format / Size | PDF / 804 Kb |
| Document Language | English |
PIN FUNCTIONS SDI (Pin 60):. LVDS Outputs. OF–/OF+ (Pins 22/23):. SCK (Pin 61):
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Text Version of Document
LTC2158-14
PIN FUNCTIONS SDI (Pin 60):
Serial Interface Data Input. In serial program-
LVDS Outputs
ming mode, (PAR/SER = 0V), SDI is the serial interface The following pins are differential LVDS outputs. The data input. Data on SDI is clocked into the mode control output current level is programmable. There is an optional registers on the rising edge of SCK. In the parallel pro- internal 100Ω termination resistor between the pins of gramming mode (PAR/SER = VDD), SDI selects 3.5mA or each LVDS output pair. 1.75mA LVDS output current (see Table 2). SDI can be driven with 1.8V to 3.3V logic.
OF–/OF+ (Pins 22/23):
Over/Underflow Digital Output. OF+ is high when an overflow or underflow has occurred.
SCK (Pin 61):
Serial Interface Clock Input. In serial The overflows for channel A and channel B are multiplexed programming mode, (PAR/SER = 0V), SCK is the serial together. interface clock input. In the parallel programming mode (PAR/SER = V
– + – +
DD), SCK can be used to place the part in the
DB0_1 /DB0_1 to DB12_13 /DB12_13 (Pins 24/25, 26/27,
low power sleep mode (see Table 2). SCK can be driven
28/29, 30/31, 34/35, 36/37, 38/39):
Channel B Double with 1.8V to 3.3V logic. Data Rate Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (DB0,
CS (Pin 62):
Serial Interface Chip Select Input. In serial DB2, DB4, DB6, DB8, DB10, DB12) appear when CLKOUT+ programming mode, (PAR/SER = 0V), CS is the serial in- is low. The odd data bits (DB1, DB3, DB5, DB7, DB9, DB11, terface chip select input. When CS is low, SCK is enabled DB13) appear when CLKOUT+ is high. for shifting data on SDI into the mode control registers. In the parallel programming mode (PAR/SER = VDD), CS
CLKOUT–/CLKOUT+ (Pins 40/41):
Data Output Clock. controls the clock duty cycle stabilizer (see Table 2). CS The digital outputs normally transition at the same time can be driven with 1.8V to 3.3V logic. as the falling and rising edges of CLKOUT+. The phase of
PAR/SER (Pin 63):
Programming Mode Selection Pin. CLKOUT+ can also be delayed relative to the digital outputs Connect to ground to enable the serial programming mode by programming the mode control registers. where CS, SCK, SDI, SDO become a serial interface that
D – + – + A0_1 /DA0_1 to DA12_13 /DA12_13 (Pins 42/43, 44/45,
control the A/D operating modes. Connect to VDD to en-
46/47, 50/51, 52/53, 54/55, 56/57):
Channel A Double able the parallel programming mode where CS, SCK, SDI Data Rate Digital Outputs. Two data bits are multiplexed become parallel logic inputs that control a reduced set of onto each differential output pair. The even data bits (DA0, the A/D operating modes. PAR/SER should be connected DA2, DA4, DA6, DA8, DA10, DA12) appear when CLKOUT+ directly to ground or the VDD of the part and not be driven is low. The odd data bits (DA1, DA3, DA5, DA7, DA9, DA11, by a logic signal. DA13) appear when CLKOUT+ is high. 215814fa For more information www.linear.com/LTC2158-14 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Typical Applications Package Description Related Parts
PIN FUNCTIONS SDI (Pin 60):
Serial Interface Data Input. In serial program-
LVDS Outputs
ming mode, (PAR/SER = 0V), SDI is the serial interface The following pins are differential LVDS outputs. The data input. Data on SDI is clocked into the mode control output current level is programmable. There is an optional registers on the rising edge of SCK. In the parallel pro- internal 100Ω termination resistor between the pins of gramming mode (PAR/SER = VDD), SDI selects 3.5mA or each LVDS output pair. 1.75mA LVDS output current (see Table 2). SDI can be driven with 1.8V to 3.3V logic.
OF–/OF+ (Pins 22/23):
Over/Underflow Digital Output. OF+ is high when an overflow or underflow has occurred.
SCK (Pin 61):
Serial Interface Clock Input. In serial The overflows for channel A and channel B are multiplexed programming mode, (PAR/SER = 0V), SCK is the serial together. interface clock input. In the parallel programming mode (PAR/SER = V
– + – +
DD), SCK can be used to place the part in the
DB0_1 /DB0_1 to DB12_13 /DB12_13 (Pins 24/25, 26/27,
low power sleep mode (see Table 2). SCK can be driven
28/29, 30/31, 34/35, 36/37, 38/39):
Channel B Double with 1.8V to 3.3V logic. Data Rate Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (DB0,
CS (Pin 62):
Serial Interface Chip Select Input. In serial DB2, DB4, DB6, DB8, DB10, DB12) appear when CLKOUT+ programming mode, (PAR/SER = 0V), CS is the serial in- is low. The odd data bits (DB1, DB3, DB5, DB7, DB9, DB11, terface chip select input. When CS is low, SCK is enabled DB13) appear when CLKOUT+ is high. for shifting data on SDI into the mode control registers. In the parallel programming mode (PAR/SER = VDD), CS
CLKOUT–/CLKOUT+ (Pins 40/41):
Data Output Clock. controls the clock duty cycle stabilizer (see Table 2). CS The digital outputs normally transition at the same time can be driven with 1.8V to 3.3V logic. as the falling and rising edges of CLKOUT+. The phase of
PAR/SER (Pin 63):
Programming Mode Selection Pin. CLKOUT+ can also be delayed relative to the digital outputs Connect to ground to enable the serial programming mode by programming the mode control registers. where CS, SCK, SDI, SDO become a serial interface that
D – + – + A0_1 /DA0_1 to DA12_13 /DA12_13 (Pins 42/43, 44/45,
control the A/D operating modes. Connect to VDD to en-
46/47, 50/51, 52/53, 54/55, 56/57):
Channel A Double able the parallel programming mode where CS, SCK, SDI Data Rate Digital Outputs. Two data bits are multiplexed become parallel logic inputs that control a reduced set of onto each differential output pair. The even data bits (DA0, the A/D operating modes. PAR/SER should be connected DA2, DA4, DA6, DA8, DA10, DA12) appear when CLKOUT+ directly to ground or the VDD of the part and not be driven is low. The odd data bits (DA1, DA3, DA5, DA7, DA9, DA11, by a logic signal. DA13) appear when CLKOUT+ is high. 215814fa For more information www.linear.com/LTC2158-14 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Typical Applications Package Description Related Parts
