Datasheet LTC2172-12, LTC2171-12, LTC2170-12 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | 12-Bit, 65Msps Low Power Quad ADCs |
| Pages / Page | 34 / 1 — FeaTures. DescripTion. 4-Channel Simultaneous Sampling ADC. 71dB SNR. … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
FeaTures. DescripTion. 4-Channel Simultaneous Sampling ADC. 71dB SNR. 90dB SFDR. applicaTions. Typical applicaTion
Model Line for this Datasheet
- LTC2170CUKG-12#PBF LTC2170CUKG-12#PBF LTC2170CUKG-12#TRPBF LTC2170CUKG-12#TRPBF LTC2170IUKG-12#PBF LTC2170IUKG-12#PBF LTC2170IUKG-12#TRPBF LTC2170IUKG-12#TRPBF
Text Version of Document
LTC2172-12/ LTC2171-12/LTC2170-12 12-Bit, 65Msps/40Msps/ 25Msps Low Power Quad ADCs
FeaTures DescripTion
n
4-Channel Simultaneous Sampling ADC
The LTC®2172-12/LTC2171-12/LTC2170-12 are 4-channel, n
71dB SNR
simultaneous sampling 12-bit A/D converters designed for n
90dB SFDR
digitizing high frequency, wide dynamic range signals. They n Low Power: 306mW/198mW/160mW Total, are perfect for demanding communications applications 77mW/50mW/40mW per Channel with AC performance that includes 71dB SNR and 90dB n Single 1.8V Supply spurious free dynamic range (SFDR). An ultralow jitter of n Serial LVDS Outputs: One or Two Bits per Channel 0.15psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 800MHz Full Power Bandwidth Sample-and-Hold DC specifications include ±0.3LSB INL (typ), ±0.1LSB n Shutdown and Nap Modes DNL (typ) and no missing codes over temperature. The n Serial SPI Port for Configuration transition noise is a low 0.3LSBRMS. n Pin-Compatible 14-Bit and 12-Bit Versions n 52-Pin (7mm × 8mm) QFN Package The digital outputs are serial LVDS to minimize the num- ber of data lines. Each channel outputs two bits at a time
applicaTions
(2-lane mode) or one bit at a time (1-lane mode). The LVDS drivers have optional internal termination and adjustable n Communications output levels to ensure clean signal integrity. n Cellular Base Stations n Software Defined Radios The ENC+ and ENC– inputs may be driven differentially n Portable Medical Imaging or single-ended with a sine wave, PECL, LVDS, TTL or n Multichannel Data Acquisition CMOS inputs. An internal clock duty cycle stabilizer al- n Nondestructive Testing lows high performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V 1.8V VDD OVDD
LTC2172-12, 65Msps, 2-Tone FFT, f
CHANNEL 1
IN = 70MHz and 75MHz
12-BIT OUT1A ANALOG S/H ADC CORE INPUT OUT1B 0 –10 CHANNEL 2 12-BIT OUT2A –20 ANALOG S/H ADC CORE INPUT OUT2B –30 DATA SERIALIZER –40 CHANNEL 3 SERIALIZED 12-BIT OUT3A –50 ANALOG S/H LVDS ADC CORE OUT3B INPUT OUTPUTS –60 –70 CHANNEL 4 OUT4A 12-BIT ANALOG S/H AMPLITUDE (dBFS) –80 ADC CORE OUT4B INPUT –90 DATA –100 CLOCK ENCODE –110 PLL OUT INPUT –120 FRAME 0 10 20 30 FREQUENCY (MHz) GND OGND 217212 TA01b 217212 TA01 21721012fb 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
FeaTures DescripTion
n
4-Channel Simultaneous Sampling ADC
The LTC®2172-12/LTC2171-12/LTC2170-12 are 4-channel, n
71dB SNR
simultaneous sampling 12-bit A/D converters designed for n
90dB SFDR
digitizing high frequency, wide dynamic range signals. They n Low Power: 306mW/198mW/160mW Total, are perfect for demanding communications applications 77mW/50mW/40mW per Channel with AC performance that includes 71dB SNR and 90dB n Single 1.8V Supply spurious free dynamic range (SFDR). An ultralow jitter of n Serial LVDS Outputs: One or Two Bits per Channel 0.15psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 800MHz Full Power Bandwidth Sample-and-Hold DC specifications include ±0.3LSB INL (typ), ±0.1LSB n Shutdown and Nap Modes DNL (typ) and no missing codes over temperature. The n Serial SPI Port for Configuration transition noise is a low 0.3LSBRMS. n Pin-Compatible 14-Bit and 12-Bit Versions n 52-Pin (7mm × 8mm) QFN Package The digital outputs are serial LVDS to minimize the num- ber of data lines. Each channel outputs two bits at a time
applicaTions
(2-lane mode) or one bit at a time (1-lane mode). The LVDS drivers have optional internal termination and adjustable n Communications output levels to ensure clean signal integrity. n Cellular Base Stations n Software Defined Radios The ENC+ and ENC– inputs may be driven differentially n Portable Medical Imaging or single-ended with a sine wave, PECL, LVDS, TTL or n Multichannel Data Acquisition CMOS inputs. An internal clock duty cycle stabilizer al- n Nondestructive Testing lows high performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V 1.8V VDD OVDD
LTC2172-12, 65Msps, 2-Tone FFT, f
CHANNEL 1
IN = 70MHz and 75MHz
12-BIT OUT1A ANALOG S/H ADC CORE INPUT OUT1B 0 –10 CHANNEL 2 12-BIT OUT2A –20 ANALOG S/H ADC CORE INPUT OUT2B –30 DATA SERIALIZER –40 CHANNEL 3 SERIALIZED 12-BIT OUT3A –50 ANALOG S/H LVDS ADC CORE OUT3B INPUT OUTPUTS –60 –70 CHANNEL 4 OUT4A 12-BIT ANALOG S/H AMPLITUDE (dBFS) –80 ADC CORE OUT4B INPUT –90 DATA –100 CLOCK ENCODE –110 PLL OUT INPUT –120 FRAME 0 10 20 30 FREQUENCY (MHz) GND OGND 217212 TA01b 217212 TA01 21721012fb 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
