Datasheet LTC2217 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | 16-Bit, 105Msps Low Noise ADC |
| Pages / Page | 32 / 1 — FEATURES. DESCRIPTION. Sample Rate: 105Msps. 81.3dBFS Noise Floor. 100dB … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
FEATURES. DESCRIPTION. Sample Rate: 105Msps. 81.3dBFS Noise Floor. 100dB SFDR. SFDR >90dB at 70MHz. 85fsRMS Jitter
Model Line for this Datasheet
Text Version of Document
LTC2217 16-Bit, 105Msps Low Noise ADC
FEATURES DESCRIPTION
■
Sample Rate: 105Msps
The LTC®2217 is a 105Msps sampling 16-bit A/D converter ■
81.3dBFS Noise Floor
designed for digitizing high frequency, wide dynamic range ■
100dB SFDR
signals with input frequencies up to 400MHz. The input ■
SFDR >90dB at 70MHz
range of the ADC is fi xed at 2.75VP-P. ■
85fsRMS Jitter
The LTC2217 is perfect for demanding communications ■
2.75VP-P Input Range
applications, with AC performance that includes 81.3dBFS ■
400MHz Full Power Bandwidth S/H
Noise Floor and 100dB spurious free dynamic range ■
Optional Internal Dither
(SFDR). Ultra low jitter of 85fsRMS allows undersampling ■
Optional Data Output Randomizer
of high input frequencies while maintaining excellent noise ■ LVDS or CMOS Outputs performance. Maximum DC specifi cations include ±3.5LSB ■ Single 3.3V Supply INL, ±1LSB DNL (no missing codes). ■ Power Dissipation: 1.19W ■ Clock Duty Cycle Stabilizer The digital output can be either differential LVDS or ■ Pin Compatible with LTC2208 single-ended CMOS. There are two format options for the ■ 64-Pin (9mm CMOS outputs: a single bus running at the full data rate or × 9mm) QFN Package demultiplexed buses running at half data rate. A separate
APPLICATIONS
output power supply allows the CMOS output swing to range from 0.5V to 3.6V. ■ Telecommunications The ENC+ and ENC– inputs may be driven differentially ■ Receivers or single-ended with a sine wave, PECL, LVDS, TTL or ■ Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- ■ Spectrum Analysis lows high performance at full speed with a wide range of ■ Imaging Systems clock duty cycles. ■ ATE , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patents Pending.
TYPICAL APPLICATION
3.3V SENSE
64k Point FFT,
OVDD
FIN = 4.9MHz, –1dBFS
1.575V INTERNAL ADC VCM 0.5V TO 3.6V COMMON MODE REFERENCE 0 2.2 BIAS VOLTAGE GENERATOR μF 1μF –10 –20 OF –30 AIN+ + CLKOUT –40 16-BIT CORRECTION OUTPUT D15 CMOS ANALOG S/H PIPELINED DRIVERS –50 LOGIC AND • OR INPUT AMP ADC CORE SHIFT REGISTER • LVDS –60 – AIN– • –70 D0 –80 AMPLITUDE (dBFS) –90 OGND –100 CLOCK/DUTY V 3.3V –110 CYCLE DD –120 CONTROL 1μF 1μF 1μF GND –130 2217 TA01 0 10 20 30 40 50 FREQUENCY (MHz) ENC + ENC – SHDN DITH MODE LVDS RAND 2217 TA01b ADC CONTROL INPUTS 2217f 1
FEATURES DESCRIPTION
■
Sample Rate: 105Msps
The LTC®2217 is a 105Msps sampling 16-bit A/D converter ■
81.3dBFS Noise Floor
designed for digitizing high frequency, wide dynamic range ■
100dB SFDR
signals with input frequencies up to 400MHz. The input ■
SFDR >90dB at 70MHz
range of the ADC is fi xed at 2.75VP-P. ■
85fsRMS Jitter
The LTC2217 is perfect for demanding communications ■
2.75VP-P Input Range
applications, with AC performance that includes 81.3dBFS ■
400MHz Full Power Bandwidth S/H
Noise Floor and 100dB spurious free dynamic range ■
Optional Internal Dither
(SFDR). Ultra low jitter of 85fsRMS allows undersampling ■
Optional Data Output Randomizer
of high input frequencies while maintaining excellent noise ■ LVDS or CMOS Outputs performance. Maximum DC specifi cations include ±3.5LSB ■ Single 3.3V Supply INL, ±1LSB DNL (no missing codes). ■ Power Dissipation: 1.19W ■ Clock Duty Cycle Stabilizer The digital output can be either differential LVDS or ■ Pin Compatible with LTC2208 single-ended CMOS. There are two format options for the ■ 64-Pin (9mm CMOS outputs: a single bus running at the full data rate or × 9mm) QFN Package demultiplexed buses running at half data rate. A separate
APPLICATIONS
output power supply allows the CMOS output swing to range from 0.5V to 3.6V. ■ Telecommunications The ENC+ and ENC– inputs may be driven differentially ■ Receivers or single-ended with a sine wave, PECL, LVDS, TTL or ■ Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- ■ Spectrum Analysis lows high performance at full speed with a wide range of ■ Imaging Systems clock duty cycles. ■ ATE , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patents Pending.
TYPICAL APPLICATION
3.3V SENSE
64k Point FFT,
OVDD
FIN = 4.9MHz, –1dBFS
1.575V INTERNAL ADC VCM 0.5V TO 3.6V COMMON MODE REFERENCE 0 2.2 BIAS VOLTAGE GENERATOR μF 1μF –10 –20 OF –30 AIN+ + CLKOUT –40 16-BIT CORRECTION OUTPUT D15 CMOS ANALOG S/H PIPELINED DRIVERS –50 LOGIC AND • OR INPUT AMP ADC CORE SHIFT REGISTER • LVDS –60 – AIN– • –70 D0 –80 AMPLITUDE (dBFS) –90 OGND –100 CLOCK/DUTY V 3.3V –110 CYCLE DD –120 CONTROL 1μF 1μF 1μF GND –130 2217 TA01 0 10 20 30 40 50 FREQUENCY (MHz) ENC + ENC – SHDN DITH MODE LVDS RAND 2217 TA01b ADC CONTROL INPUTS 2217f 1
