Datasheet LTC1799 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 1kHz to 33MHz Resistor Set SOT-23 Oscillator |
| Pages / Page | 14 / 5 — pin FuncTions. V+ (Pin 1):. GND (Pin 2):. SET (Pin 3):. OUT (Pin 5):. DIV … |
| File Format / Size | PDF / 238 Kb |
| Document Language | English |
pin FuncTions. V+ (Pin 1):. GND (Pin 2):. SET (Pin 3):. OUT (Pin 5):. DIV (Pin 4):. block DiagraM
Model Line for this Datasheet
Text Version of Document
LTC1799
pin FuncTions V+ (Pin 1):
Voltage Supply (2.7V ≤ V+ ≤ 5.5V). This sup- Floating Pin 4 divides the master oscillator by 10. Pin 4 ply must be kept free from noise and ripple. It should be should be tied to V+ for the ÷100 setting, the lowest fre- bypassed directly to a ground plane with a 0.1µF capacitor. quency range. To detect a floating DIV pin, the LTC1799
GND (Pin 2):
Ground. Should be tied to a ground plane attempts to pull the pin toward midsupply. This is realized for best performance. with two internal current sources, one tied to V+ and Pin 4 and the other one tied to ground and Pin 4. Therefore,
SET (Pin 3):
Frequency-Setting Resistor Input. The value driving the DIV pin high requires sourcing approximately of the resistor connected between this pin and V+ deter- 5µA. Likewise, driving DIV low requires sinking 5µA. mines the oscillator frequency. The voltage on this pin is When Pin 4 is floated, preferably it should be bypassed held by the LTC1799 to approximately 1.13V below the by a 1nF capacitor to ground or it should be surrounded V+ voltage. For best performance, use a precision metal by a ground shield to prevent excessive coupling from film resistor with a value between 10k and 200k and limit other PCB traces. the capacitance on this pin to less than 10pF.
OUT (Pin 5):
Oscillator Output. This pin can drive 5kΩ
DIV (Pin 4):
Divider-Setting Input. This three-state input and/or 10pF loads. Larger loads may cause inaccuracies selects among three divider settings, determining the due to supply bounce at high frequencies. Transients will value of N in the frequency equation. Pin 4 should be tied not cause latchup if the current into/out of the OUT pin is to GND for the ÷1 setting, the highest frequency range. limited to 50mA.
block DiagraM
VRES = 1.13V ±25% V+ (V+ – V PROGRAMMABLE SET) OUT 1 DIVIDER 5 + (÷1, 10 OR 100) RSET V+ GAIN = 1 I MASTER OSCILLATOR RES SET 3 – DIVIDER I 5µA + RES ƒ SELECT – V MO = 100MHz • kΩ • BIAS (V+ – VSET) DIV 2 GND THREE-STATE I 4 RES INPUT DETECT 5µA GND 1799 BD 1799fd For more information www.linear.com/LTC1799 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Theory of Operation Applications Information Typical Application Package Description Revision History Typical Applications
pin FuncTions V+ (Pin 1):
Voltage Supply (2.7V ≤ V+ ≤ 5.5V). This sup- Floating Pin 4 divides the master oscillator by 10. Pin 4 ply must be kept free from noise and ripple. It should be should be tied to V+ for the ÷100 setting, the lowest fre- bypassed directly to a ground plane with a 0.1µF capacitor. quency range. To detect a floating DIV pin, the LTC1799
GND (Pin 2):
Ground. Should be tied to a ground plane attempts to pull the pin toward midsupply. This is realized for best performance. with two internal current sources, one tied to V+ and Pin 4 and the other one tied to ground and Pin 4. Therefore,
SET (Pin 3):
Frequency-Setting Resistor Input. The value driving the DIV pin high requires sourcing approximately of the resistor connected between this pin and V+ deter- 5µA. Likewise, driving DIV low requires sinking 5µA. mines the oscillator frequency. The voltage on this pin is When Pin 4 is floated, preferably it should be bypassed held by the LTC1799 to approximately 1.13V below the by a 1nF capacitor to ground or it should be surrounded V+ voltage. For best performance, use a precision metal by a ground shield to prevent excessive coupling from film resistor with a value between 10k and 200k and limit other PCB traces. the capacitance on this pin to less than 10pF.
OUT (Pin 5):
Oscillator Output. This pin can drive 5kΩ
DIV (Pin 4):
Divider-Setting Input. This three-state input and/or 10pF loads. Larger loads may cause inaccuracies selects among three divider settings, determining the due to supply bounce at high frequencies. Transients will value of N in the frequency equation. Pin 4 should be tied not cause latchup if the current into/out of the OUT pin is to GND for the ÷1 setting, the highest frequency range. limited to 50mA.
block DiagraM
VRES = 1.13V ±25% V+ (V+ – V PROGRAMMABLE SET) OUT 1 DIVIDER 5 + (÷1, 10 OR 100) RSET V+ GAIN = 1 I MASTER OSCILLATOR RES SET 3 – DIVIDER I 5µA + RES ƒ SELECT – V MO = 100MHz • kΩ • BIAS (V+ – VSET) DIV 2 GND THREE-STATE I 4 RES INPUT DETECT 5µA GND 1799 BD 1799fd For more information www.linear.com/LTC1799 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Theory of Operation Applications Information Typical Application Package Description Revision History Typical Applications
