Datasheet LTC2225 (Analog Devices) - 10

LTC2225
U U W U APPLICATIO S I FOR ATIO Aperture Delay Time
the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the The time from when CLK reaches mid-supply to the instant third, fourth and fifth stages, resulting in a fifth stage that the input signal is held by the sample and hold circuit. residue that is sent to the sixth stage ADC for final
Aperture Delay Jitter
evaluation. The variation in the aperture delay time from conversion to Each ADC stage following the first has additional range to conversion. This random variation will result in noise accommodate flash and amplifier offset errors. Results when sampling an AC input. The signal to noise ratio due from all of the ADC stages are digitally synchronized such to the jitter alone will be: that the results can be properly combined in the correction logic before being sent to the output buffer. SNRJITTER = –20log (2π • fIN • tJITTER)
SAMPLE/HOLD OPERATION AND INPUT DRIVE CONVERTER OPERATION
As shown in Figure 1, the LTC2225 is a CMOS pipelined
Sample/Hold Operation
multistep converter. The converter has six pipelined ADC Figure 2 shows an equivalent circuit for the LTC2225 stages; a sampled analog input will result in a digitized CMOS differential sample-and-hold. The analog inputs are value five cycles later (see the Timing Diagram section). connected to the sampling capacitors (CSAMPLE) through For optimal AC performance the analog inputs should be NMOS transistors. The capacitors shown attached to each driven differentially. For cost sensitive applications, the input (CPARASITIC) are the summation of all other capaci- analog inputs can be driven single-ended with slightly tance associated with each input. worse harmonic distortion. The CLK input is single-ended. The LTC2225 has two phases of operation, determined by LTC2225 VDD the state of the CLK input pin. CSAMPLE 4pF 15Ω Each pipelined stage shown in Figure 1 contains an ADC, AIN+ CPARASITIC a reconstruction DAC and an interstage residue amplifier. 1pF VDD In operation, the ADC quantizes the input to the stage and CSAMPLE 4pF the quantized value is subtracted from the input by the 15Ω AIN– DAC to produce a residue. The residue is amplified and CPARASITIC 1pF output by the residue amplifier. Successive stages operate VDD out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue CLK and vice versa. 2225 F02 When CLK is low, the analog input is sampled differentially
Figure 2. Equivalent Input Circuit
directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant During the sample phase when CLK is low, the transistors that CLK transitions from low to high, the sampled input is connect the analog inputs to the sampling capacitors and held. While CLK is high, the held input voltage is buffered they charge to and track the differential input voltage. by the S/H amplifier which drives the first pipelined ADC When CLK transitions from low to high, the sampled input stage. The first stage acquires the output of the S/H during voltage is held on the sampling capacitors. During the hold this high phase of CLK. When CLK goes back low, the first phase when CLK is high, the sampling capacitors are stage produces its residue which is acquired by the disconnected from the input and the held voltage is passed second stage. At the same time, the input S/H goes back to the ADC core for processing. As CLK transitions from to acquiring the analog input. When CLK goes back high, high to low, the inputs are reconnected to the sampling 2225fa 10