Datasheet LTC2241-12 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 12-Bit, 210Msps ADC |
| Pages / Page | 30 / 10 — pin FuncTions (LVDS Mode). OGND (Pins 25, 33, 41, 50):. AIN+ (Pins 1, … |
| File Format / Size | PDF / 753 Kb |
| Document Language | English |
pin FuncTions (LVDS Mode). OGND (Pins 25, 33, 41, 50):. AIN+ (Pins 1, 2):. OVDD (Pins 26, 34, 42, 49):. AIN– (Pins 3, 4):
Model Line for this Datasheet
Text Version of Document
LTC2241-12
pin FuncTions (LVDS Mode) OGND (Pins 25, 33, 41, 50):
Output Driver Ground.
AIN+ (Pins 1, 2):
Positive Differential Analog Input.
OVDD (Pins 26, 34, 42, 49):
Positive Supply for the Out-
AIN– (Pins 3, 4):
Negative Differential Analog Input. put Drivers. Bypass to ground with 0.1µF ceramic chip capacitor.
REFHA (Pins 5, 6):
ADC High Reference. Bypass to Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12
CLKOUT–/CLKOUT+ (Pins 35 to 36):
LVDS Data Valid with a 2.2µF ceramic capacitor and to ground with 1µF Output. Latch data on rising edge of CLKOUT–, falling ceramic capacitor. edge of CLKOUT+.
REFLB (Pins 7, 8):
ADC Low Reference. Bypass to Pins
OF–/OF+ (Pins 55 to 56):
LVDS Over/Under Flow Output. 5, 6 with 0.1µF ceramic chip capacitor. Do not connect to High when an over or under flow has occurred. Pins 11, 12.
LVDS (Pin 57):
Output Mode Selection Pin. Connecting
REFHB (Pins 9, 10):
ADC High Reference. Bypass to Pins LVDS to 0V selects full rate CMOS mode. Connecting LVDS 11, 12 with 0.1µF ceramic chip capacitor. Do not connect to 1/3VDD selects demux CMOS mode with simultaneous to Pins 5, 6. update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to V
REFLA (Pins 11, 12):
ADC Low Reference. Bypass to DD selects LVDS mode. Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6 with a 2.2µF ceramic capacitor and to ground with 1µF
MODE (Pin 58):
Output Format and Clock Duty Cycle ceramic capacitor. Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle
VDD (Pins 13, 14, 15, 62, 63):
2.5V Supply. Bypass to stabilizer off. Connecting MODE to 1/3V GND with 0.1µF ceramic chip capacitors. DD selects offset binary output format and turns the clock duty cycle stabilizer
GND (Pins 16, 61, 64):
ADC Power Ground. on. Connecting MODE to 2/3VDD selects 2’s complement
ENC+ (Pin 17):
Encode Input. Conversion starts on the output format and turns the clock duty cycle stabilizer on. positive edge. Connecting MODE to VDD selects 2’s complement output
ENC– (Pin 18):
Encode Complement Input. Conversion format and turns the clock duty cycle stabilizer off. starts on the negative edge. Bypass to ground with 0.1µF
SENSE (Pin 59):
Reference Programming Pin. Connecting ceramic for single-ended encode signal. SENSE to VCM selects the internal reference and a ±0.5V
SHDN (Pin 19):
Shutdown Mode Selection Pin. Connecting input range. Connecting SENSE to VDD selects the internal SHDN to GND and OE to GND results in normal operation reference and a ±1V input range. An external reference with the outputs enabled. Connecting SHDN to GND and greater than 0.5V and less than 1V applied to SENSE OE to V selects an input range of ±VSENSE. ±1V is the largest valid DD results in normal operation with the outputs at high impedance. Connecting SHDN to V input range. DD and OE to GND results in nap mode with the outputs at high impedance.
VCM (Pin 60):
1.25V Output and Input Common Mode Connecting SHDN to VDD and OE to VDD results in sleep Bias. Bypass to ground with 2.2µF ceramic chip capacitor. mode with the outputs at high impedance.
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The
OE (Pin 20):
Output Enable Pin. Refer to SHDN pin function. exposed pad on the bottom of the package needs to be
D0–/D0+ to D11–/D11+ (Pins 21, 22, 23, 24, 27, 28, 29,
soldered to ground.
30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54):
LVDS Digital Outputs. All LVDS outputs re- quire differential 100Ω termination resistors at the LVDS receiver. D11–/D11+ is the MSB. 224112fc 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Package Description Revision History Related Parts
pin FuncTions (LVDS Mode) OGND (Pins 25, 33, 41, 50):
Output Driver Ground.
AIN+ (Pins 1, 2):
Positive Differential Analog Input.
OVDD (Pins 26, 34, 42, 49):
Positive Supply for the Out-
AIN– (Pins 3, 4):
Negative Differential Analog Input. put Drivers. Bypass to ground with 0.1µF ceramic chip capacitor.
REFHA (Pins 5, 6):
ADC High Reference. Bypass to Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12
CLKOUT–/CLKOUT+ (Pins 35 to 36):
LVDS Data Valid with a 2.2µF ceramic capacitor and to ground with 1µF Output. Latch data on rising edge of CLKOUT–, falling ceramic capacitor. edge of CLKOUT+.
REFLB (Pins 7, 8):
ADC Low Reference. Bypass to Pins
OF–/OF+ (Pins 55 to 56):
LVDS Over/Under Flow Output. 5, 6 with 0.1µF ceramic chip capacitor. Do not connect to High when an over or under flow has occurred. Pins 11, 12.
LVDS (Pin 57):
Output Mode Selection Pin. Connecting
REFHB (Pins 9, 10):
ADC High Reference. Bypass to Pins LVDS to 0V selects full rate CMOS mode. Connecting LVDS 11, 12 with 0.1µF ceramic chip capacitor. Do not connect to 1/3VDD selects demux CMOS mode with simultaneous to Pins 5, 6. update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to V
REFLA (Pins 11, 12):
ADC Low Reference. Bypass to DD selects LVDS mode. Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6 with a 2.2µF ceramic capacitor and to ground with 1µF
MODE (Pin 58):
Output Format and Clock Duty Cycle ceramic capacitor. Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle
VDD (Pins 13, 14, 15, 62, 63):
2.5V Supply. Bypass to stabilizer off. Connecting MODE to 1/3V GND with 0.1µF ceramic chip capacitors. DD selects offset binary output format and turns the clock duty cycle stabilizer
GND (Pins 16, 61, 64):
ADC Power Ground. on. Connecting MODE to 2/3VDD selects 2’s complement
ENC+ (Pin 17):
Encode Input. Conversion starts on the output format and turns the clock duty cycle stabilizer on. positive edge. Connecting MODE to VDD selects 2’s complement output
ENC– (Pin 18):
Encode Complement Input. Conversion format and turns the clock duty cycle stabilizer off. starts on the negative edge. Bypass to ground with 0.1µF
SENSE (Pin 59):
Reference Programming Pin. Connecting ceramic for single-ended encode signal. SENSE to VCM selects the internal reference and a ±0.5V
SHDN (Pin 19):
Shutdown Mode Selection Pin. Connecting input range. Connecting SENSE to VDD selects the internal SHDN to GND and OE to GND results in normal operation reference and a ±1V input range. An external reference with the outputs enabled. Connecting SHDN to GND and greater than 0.5V and less than 1V applied to SENSE OE to V selects an input range of ±VSENSE. ±1V is the largest valid DD results in normal operation with the outputs at high impedance. Connecting SHDN to V input range. DD and OE to GND results in nap mode with the outputs at high impedance.
VCM (Pin 60):
1.25V Output and Input Common Mode Connecting SHDN to VDD and OE to VDD results in sleep Bias. Bypass to ground with 2.2µF ceramic chip capacitor. mode with the outputs at high impedance.
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The
OE (Pin 20):
Output Enable Pin. Refer to SHDN pin function. exposed pad on the bottom of the package needs to be
D0–/D0+ to D11–/D11+ (Pins 21, 22, 23, 24, 27, 28, 29,
soldered to ground.
30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54):
LVDS Digital Outputs. All LVDS outputs re- quire differential 100Ω termination resistors at the LVDS receiver. D11–/D11+ is the MSB. 224112fc 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Package Description Revision History Related Parts
