Datasheet LTC2269 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 16-Bit, 20Msps Low Noise ADC |
| Pages / Page | 32 / 8 — ELECTRICAL CHARACTERISTICS. Note 1:. Note 5:. Note 6:. Note 2:. Note 3:. … |
| File Format / Size | PDF / 775 Kb |
| Document Language | English |
ELECTRICAL CHARACTERISTICS. Note 1:. Note 5:. Note 6:. Note 2:. Note 3:. Note 7:. Note 4:. Note 8:. Note 9:. Note 10:. TIMING DIAGRAMS
Model Line for this Datasheet
Text Version of Document
LTC2269
ELECTRICAL CHARACTERISTICS Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
VDD = OVDD = 1.8V, fSAMPLE = 20MHz LVDS outputs, differential may cause permanent damage to the device. Exposure to any Absolute ENC+/ENC– = 2VP-P sine wave, input range = 2.1VP-P with differential drive, Maximum Rating condition for extended periods may affect device unless otherwise noted. reliability and lifetime.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a
Note 2:
All voltage values are with respect to GND with GND and OGND best fit straight line to the transfer curve. The deviation is measured from shorted (unless otherwise noted). the center of the quantization band.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 7:
Offset error is the offset voltage measured from –0.5 LSB when will be clamped by internal diodes. This product can handle input currents the output code flickers between 0000 0000 0000 0000 and 1111 1111 of greater than 100mA below GND or above VDD without latchup. 1111 1111 in 2’s complement output mode.
Note 4:
When these pin voltages are taken below GND they will be
Note 8:
Guaranteed by design, not subject to test. clamped by internal diodes. When these pin voltages are taken above VDD
Note 9:
VDD = 1.8V, fSAMPLE = 20MHz CMOS outputs, ENC+ = single-ended they will not be clamped by internal diodes. This product can handle input 1.8V square wave, ENC– = 0V, input range = 2.1VP-P with differential drive, currents of greater than 100mA below GND without latchup. 5pF load on each digital output unless otherwise noted.
Note 10:
Recommended operating conditions.
TIMING DIAGRAMS Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels
tAP N + 2 N + 4 ANALOG N INPUT N + 3 tH N + 1 tL ENC– ENC+ tD D0–D15, OF N – 6 N – 5 N – 4 N – 3 N – 2 tC CLKOUT+ CLKOUT– 2269 TD01 2269f 8
ELECTRICAL CHARACTERISTICS Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
VDD = OVDD = 1.8V, fSAMPLE = 20MHz LVDS outputs, differential may cause permanent damage to the device. Exposure to any Absolute ENC+/ENC– = 2VP-P sine wave, input range = 2.1VP-P with differential drive, Maximum Rating condition for extended periods may affect device unless otherwise noted. reliability and lifetime.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a
Note 2:
All voltage values are with respect to GND with GND and OGND best fit straight line to the transfer curve. The deviation is measured from shorted (unless otherwise noted). the center of the quantization band.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 7:
Offset error is the offset voltage measured from –0.5 LSB when will be clamped by internal diodes. This product can handle input currents the output code flickers between 0000 0000 0000 0000 and 1111 1111 of greater than 100mA below GND or above VDD without latchup. 1111 1111 in 2’s complement output mode.
Note 4:
When these pin voltages are taken below GND they will be
Note 8:
Guaranteed by design, not subject to test. clamped by internal diodes. When these pin voltages are taken above VDD
Note 9:
VDD = 1.8V, fSAMPLE = 20MHz CMOS outputs, ENC+ = single-ended they will not be clamped by internal diodes. This product can handle input 1.8V square wave, ENC– = 0V, input range = 2.1VP-P with differential drive, currents of greater than 100mA below GND without latchup. 5pF load on each digital output unless otherwise noted.
Note 10:
Recommended operating conditions.
TIMING DIAGRAMS Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels
tAP N + 2 N + 4 ANALOG N INPUT N + 3 tH N + 1 tL ENC– ENC+ tD D0–D15, OF N – 6 N – 5 N – 4 N – 3 N – 2 tC CLKOUT+ CLKOUT– 2269 TD01 2269f 8
