Datasheet LTC2273, LTC2272 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | 16-Bit, 80Msps Serial Output ADC (JESD204) |
| Pages / Page | 44 / 1 — FEATURES. DESCRIPTION. High Speed Serial Interface (JESD204). Sample … |
| File Format / Size | PDF / 791 Kb |
| Document Language | English |
FEATURES. DESCRIPTION. High Speed Serial Interface (JESD204). Sample Rate: 80Msps/65Msps. 77.7dBFS Noise Floor. 100dB SFDR
Model Line for this Datasheet
Text Version of Document
LTC2273/LTC2272 16-Bit, 80Msps/65Msps Serial Output ADC
FEATURES DESCRIPTION
n
High Speed Serial Interface (JESD204)
The LTC®2273/LTC2272 are 80Msps/65Msps, 16-bit A/D n
Sample Rate: 80Msps/65Msps
converters with a high speed serial interface. They are n
77.7dBFS Noise Floor
designed for digitizing high frequency, wide dynamic n
100dB SFDR
range signals with an input bandwidth of 700MHz. The n
SFDR >90dB at 140MHz (1.5VP-P Input Range)
input range of the ADC can be optimized using the PGA n
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
front end. The output data is serialized according to the n
700MHz Full Power Bandwidth S/H
JEDEC serial interface for data converters specifi cation n
Optional Internal Dither
(JESD204). n Single 3.3V Supply The LTC2273/LTC2272 are perfect for demanding applica- n Power Dissipation: 1100mW/990mW tions where it is desirable to isolate the sensitive analog n Clock Duty Cycle Stabilizer circuits from the noisy digital logic. The AC performance n Pin Compatible Family includes a 77.7dB Noise Floor and 100dB spurious free 105Msps: LTC2274 dynamic range (SFDR). Ultra low internal jitter of 80fs 80Msps: LTC2273 RMS allows undersampling of high input frequencies 65Msps: LTC2272 with excellent noise performance. Maximum DC specs n 40-Pin 6mm × 6mm QFN Package include ±4.5LSB INL and ±1LSB DNL (no missing codes) over temperature.
APPLICATIONS
The encode clock inputs, ENC+ and ENC–, may be driven n Telecommunications differentially or single-ended with a sine wave, PECL, n Receivers LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer n Cellular Base Stations allows high performance at full speed with a wide range n Spectrum Analysis of clock duty cycles. n Imaging Systems L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n ATE
TYPICAL APPLICATION
3.3V FAM SENSE SYNC+
128k Point FFT, fIN = 4.93MHz,
1.25V INTERNAL ADC SYNC– V
–1dBFS, PGA = 0
CM 8B/10B ASIC OR FPGA COMMON MODE REFERENCE ENCODER 1.2V TO 3.3V BIAS VOLTAGE GENERATOR OVDD 0 2.2μF –10 16 20 0.1μF 50Ω –20 –30 50Ω –40 CMLOUT+ + –50 A + IN (dBFS) + SERIAL –60 16-BIT SERIALIZER ANALOG RECEIVER S/H CORRECTION PIPELINED –70 INPUT AMP – ADC CORE LOGIC CMLOUT– –80 – – A AMPLITUDE –90 IN CLOCK –100 3.3V –110 VDD CLOCK/DUTY SCRAMBLER/ 20X –120 CYCLE PATTERN PLL –130 CONTROL GENERATOR 0.1μF 0.1μF 0 10 20 30 40 GND FREQUENCY (MHz) 22732 TA01 22732 G04 ENC+ ENC– PGA DITH MSBINV SHDN PAT1 PAT0 SCRAM SRR1 SRR0 22732fa 1
FEATURES DESCRIPTION
n
High Speed Serial Interface (JESD204)
The LTC®2273/LTC2272 are 80Msps/65Msps, 16-bit A/D n
Sample Rate: 80Msps/65Msps
converters with a high speed serial interface. They are n
77.7dBFS Noise Floor
designed for digitizing high frequency, wide dynamic n
100dB SFDR
range signals with an input bandwidth of 700MHz. The n
SFDR >90dB at 140MHz (1.5VP-P Input Range)
input range of the ADC can be optimized using the PGA n
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
front end. The output data is serialized according to the n
700MHz Full Power Bandwidth S/H
JEDEC serial interface for data converters specifi cation n
Optional Internal Dither
(JESD204). n Single 3.3V Supply The LTC2273/LTC2272 are perfect for demanding applica- n Power Dissipation: 1100mW/990mW tions where it is desirable to isolate the sensitive analog n Clock Duty Cycle Stabilizer circuits from the noisy digital logic. The AC performance n Pin Compatible Family includes a 77.7dB Noise Floor and 100dB spurious free 105Msps: LTC2274 dynamic range (SFDR). Ultra low internal jitter of 80fs 80Msps: LTC2273 RMS allows undersampling of high input frequencies 65Msps: LTC2272 with excellent noise performance. Maximum DC specs n 40-Pin 6mm × 6mm QFN Package include ±4.5LSB INL and ±1LSB DNL (no missing codes) over temperature.
APPLICATIONS
The encode clock inputs, ENC+ and ENC–, may be driven n Telecommunications differentially or single-ended with a sine wave, PECL, n Receivers LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer n Cellular Base Stations allows high performance at full speed with a wide range n Spectrum Analysis of clock duty cycles. n Imaging Systems L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n ATE
TYPICAL APPLICATION
3.3V FAM SENSE SYNC+
128k Point FFT, fIN = 4.93MHz,
1.25V INTERNAL ADC SYNC– V
–1dBFS, PGA = 0
CM 8B/10B ASIC OR FPGA COMMON MODE REFERENCE ENCODER 1.2V TO 3.3V BIAS VOLTAGE GENERATOR OVDD 0 2.2μF –10 16 20 0.1μF 50Ω –20 –30 50Ω –40 CMLOUT+ + –50 A + IN (dBFS) + SERIAL –60 16-BIT SERIALIZER ANALOG RECEIVER S/H CORRECTION PIPELINED –70 INPUT AMP – ADC CORE LOGIC CMLOUT– –80 – – A AMPLITUDE –90 IN CLOCK –100 3.3V –110 VDD CLOCK/DUTY SCRAMBLER/ 20X –120 CYCLE PATTERN PLL –130 CONTROL GENERATOR 0.1μF 0.1μF 0 10 20 30 40 GND FREQUENCY (MHz) 22732 TA01 22732 G04 ENC+ ENC– PGA DITH MSBINV SHDN PAT1 PAT0 SCRAM SRR1 SRR0 22732fa 1
