Datasheet LTC2312-12 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 12-Bit, 500ksps Serial Sampling ADC in TSOT |
| Pages / Page | 22 / 5 — Dc TiMing characTerisTics The. denotes the specifications which apply … |
| File Format / Size | PDF / 520 Kb |
| Document Language | English |
Dc TiMing characTerisTics The. denotes the specifications which apply over the full operating
Model Line for this Datasheet
- LTC2312CTS8-12#PBF LTC2312CTS8-12#TRMPBF LTC2312CTS8-12#TRMPBF LTC2312CTS8-12#TRPBF LTC2312CTS8-12#TRPBF LTC2312HTS8-12#PBF LTC2312HTS8-12#TRMPBF LTC2312HTS8-12#TRMPBF LTC2312HTS8-12#TRPBF LTC2312HTS8-12#TRPBF LTC2312ITS8-12#PBF LTC2312ITS8-12#TRMPBF LTC2312ITS8-12#TRMPBF LTC2312ITS8-12#TRPBF LTC2312ITS8-12#TRPBF
Text Version of Document
LTC2312-12
a Dc TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency (Notes 7, 8) l 500 kHz fSCK Shift Clock Frequency (Notes 7, 8) l 20 MHz tSCK Shift Clock Period l 50 ns tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV l 2000 ns tCONV Conversion Time l 1400 ns tACQ Acquisition Time l 600 ns t1 Minimum CONV Pulse Width (Note 7), Valid for Nap and Sleep Modes Only l 10 ns t2 SCK↑ Setup Time After CONV↓ (Note 7), Valid for Nap and Sleep Modes Only l 10 ns t3 SDO Enable Time After CONV↓ (Notes 7, 8) l 10 ns t4 SDO Data Valid Access Time after SCK↓ (Notes 7, 8, 9) l 11 ns t5 SCK Low Time l 10 ns t6 SCK High Time l 10 ns t7 SDO Data Valid Hold Time After SCK↓ (Notes 7, 8, 9) l 1 ns t8 SDO into Hi-Z State Time After CONV↑ (Notes 7, 8, 10) l 3 10 ns t9 CONV↑ Quiet Time After 12th SCK↓ (Note 7) l 15 ns tWAKE_NAP Power-Up Time from Nap Mode See Nap Mode Section 50 ns tWAKE_SLEEP Power-Up Time from Sleep Mode See Sleep Mode Section 1.1 ms
Note 1.
Stresses beyond those listed under Absolute Maximum Ratings
Note 6.
Typical RMS noise at code transitions. may cause permanent damage to the device. Exposure to any Absolute
Note 7.
Parameter tested and guaranteed at OVDD = 2.5V. All input signals Maximum Rating condition for extended periods may affect device are specified with tr = tf = 1ns (10% to 90% of OVDD) and timed from a reliability and lifetime. voltage level of OVDD/2.
Note 2
. All voltage values are with respect to ground.
Note 8.
All timing specifications given are with a 10pF capacitance load.
Note 3.
When these pin voltages are taken below ground or above VDD Load capacitances greater than this will require a digital buffer. (AIN, REF) or OVDD (SCK, CONV, SDO) they will be clamped by internal
Note 9.
The time required for the output to cross the VOH or VOL voltage. diodes. This product can handle input currents up to 100mA below ground
Note 10.
Guaranteed by design, not subject to test. or above VDD or OVDD without latch-up.
Note 11.
Recommended operating conditions.
Note 4.
VDD = 5V, OVDD = 2.5V, fSMPL = 500kHz, fSCK = 20MHz, AIN = –1dBFS and internal reference unless otherwise noted.
Note 5.
Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 231212fa For more information www.linear.com/LTC2312-12 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input/Output Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Applications Information Package Description Revision History Typical Application Related Parts
a Dc TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency (Notes 7, 8) l 500 kHz fSCK Shift Clock Frequency (Notes 7, 8) l 20 MHz tSCK Shift Clock Period l 50 ns tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV l 2000 ns tCONV Conversion Time l 1400 ns tACQ Acquisition Time l 600 ns t1 Minimum CONV Pulse Width (Note 7), Valid for Nap and Sleep Modes Only l 10 ns t2 SCK↑ Setup Time After CONV↓ (Note 7), Valid for Nap and Sleep Modes Only l 10 ns t3 SDO Enable Time After CONV↓ (Notes 7, 8) l 10 ns t4 SDO Data Valid Access Time after SCK↓ (Notes 7, 8, 9) l 11 ns t5 SCK Low Time l 10 ns t6 SCK High Time l 10 ns t7 SDO Data Valid Hold Time After SCK↓ (Notes 7, 8, 9) l 1 ns t8 SDO into Hi-Z State Time After CONV↑ (Notes 7, 8, 10) l 3 10 ns t9 CONV↑ Quiet Time After 12th SCK↓ (Note 7) l 15 ns tWAKE_NAP Power-Up Time from Nap Mode See Nap Mode Section 50 ns tWAKE_SLEEP Power-Up Time from Sleep Mode See Sleep Mode Section 1.1 ms
Note 1.
Stresses beyond those listed under Absolute Maximum Ratings
Note 6.
Typical RMS noise at code transitions. may cause permanent damage to the device. Exposure to any Absolute
Note 7.
Parameter tested and guaranteed at OVDD = 2.5V. All input signals Maximum Rating condition for extended periods may affect device are specified with tr = tf = 1ns (10% to 90% of OVDD) and timed from a reliability and lifetime. voltage level of OVDD/2.
Note 2
. All voltage values are with respect to ground.
Note 8.
All timing specifications given are with a 10pF capacitance load.
Note 3.
When these pin voltages are taken below ground or above VDD Load capacitances greater than this will require a digital buffer. (AIN, REF) or OVDD (SCK, CONV, SDO) they will be clamped by internal
Note 9.
The time required for the output to cross the VOH or VOL voltage. diodes. This product can handle input currents up to 100mA below ground
Note 10.
Guaranteed by design, not subject to test. or above VDD or OVDD without latch-up.
Note 11.
Recommended operating conditions.
Note 4.
VDD = 5V, OVDD = 2.5V, fSMPL = 500kHz, fSCK = 20MHz, AIN = –1dBFS and internal reference unless otherwise noted.
Note 5.
Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 231212fa For more information www.linear.com/LTC2312-12 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input/Output Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Applications Information Package Description Revision History Typical Application Related Parts
