Datasheet LTC2312-14 (Analog Devices) - 11
| Manufacturer | Analog Devices |
| Description | 14-Bit, 500ksps Serial Sampling ADC in TSOT |
| Pages / Page | 22 / 11 — APPLICATIONS INFORMATION. Figure 5. LTC2312-14 Serial Interface Timing … |
| File Format / Size | PDF / 635 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Figure 5. LTC2312-14 Serial Interface Timing Diagram (SCK Low During tCONV)
Model Line for this Datasheet
- LTC2312CTS8-14#PBF LTC2312CTS8-14#TRMPBF LTC2312CTS8-14#TRMPBF LTC2312CTS8-14#TRPBF LTC2312CTS8-14#TRPBF LTC2312HTS8-14#PBF LTC2312HTS8-14#TRMPBF LTC2312HTS8-14#TRMPBF LTC2312HTS8-14#TRPBF LTC2312HTS8-14#TRPBF LTC2312ITS8-14#PBF LTC2312ITS8-14#TRMPBF LTC2312ITS8-14#TRMPBF LTC2312ITS8-14#TRPBF LTC2312ITS8-14#TRPBF
Text Version of Document
LTC2312-14
APPLICATIONS INFORMATION
t9 CONV tACQ-MIN = 13.5 • tSCK + t2 + t9 tCONV-MIN tACQ t2 t6 SCK 1 2 3 4 12 13 14 t5 t8 t3 t4 t7 HI-Z STATE SDO B13 B12 B11 B10 B1 B0 0 (MSB) tTHROUGHPUT 231214 F05
Figure 5. LTC2312-14 Serial Interface Timing Diagram (SCK Low During tCONV)
t9 CONV tACQ-MIN = 13.5 • tSCK + t2 + t9 tCONV-MIN tACQ t2 t6 SCK 1 2 3 4 13 14 t5 t3 t t 8 4 t7 HI-Z STATE SDO B13 B12 B11 B10 B1 B0 0 (MSB) tTHROUGHPUT 231214 F06
Figure 6. LTC2312-14 Serial Interface Timing Diagram (SCK High During tCONV)
t9 t2 CONV CONVERT POWER-DOWN tCONV-MIN NAP MODE tACQ SCK t t 8 3 HI-Z STATE SDO B13 B12 t (MSB) CONV > tCONV-MIN 231214 F07
Figure 7. LTC2312-14 Nap Mode Power-Down Following Conversion for tCONV > tCONV-MIN
231214fa For more information www.linear.com/LTC2312-14 11 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input/Output Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Applications Information Package Description Related Parts
APPLICATIONS INFORMATION
t9 CONV tACQ-MIN = 13.5 • tSCK + t2 + t9 tCONV-MIN tACQ t2 t6 SCK 1 2 3 4 12 13 14 t5 t8 t3 t4 t7 HI-Z STATE SDO B13 B12 B11 B10 B1 B0 0 (MSB) tTHROUGHPUT 231214 F05
Figure 5. LTC2312-14 Serial Interface Timing Diagram (SCK Low During tCONV)
t9 CONV tACQ-MIN = 13.5 • tSCK + t2 + t9 tCONV-MIN tACQ t2 t6 SCK 1 2 3 4 13 14 t5 t3 t t 8 4 t7 HI-Z STATE SDO B13 B12 B11 B10 B1 B0 0 (MSB) tTHROUGHPUT 231214 F06
Figure 6. LTC2312-14 Serial Interface Timing Diagram (SCK High During tCONV)
t9 t2 CONV CONVERT POWER-DOWN tCONV-MIN NAP MODE tACQ SCK t t 8 3 HI-Z STATE SDO B13 B12 t (MSB) CONV > tCONV-MIN 231214 F07
Figure 7. LTC2312-14 Nap Mode Power-Down Following Conversion for tCONV > tCONV-MIN
231214fa For more information www.linear.com/LTC2312-14 11 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input/Output Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Applications Information Package Description Related Parts
