Datasheet LTC2335-16 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 16-Bit, 1Msps 8-Channel Differential ±10.24V Input SoftSpan ADC with Wide Input Common Mode Range |
| Pages / Page | 40 / 8 — aDc TiMing characTerisTics Note 1:. Note 11:. Note 12:. Note 2:. Note 3:. … |
| File Format / Size | PDF / 2.2 Mb |
| Document Language | English |
aDc TiMing characTerisTics Note 1:. Note 11:. Note 12:. Note 2:. Note 3:. Note 4:. Note 13:. Note 5:. Note 14:. Note 6:. Note 15:. Note 7:
Model Line for this Datasheet
Text Version of Document
LTC2335-16
aDc TiMing characTerisTics Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 11:
Guaranteed by design, not subject to test. may cause permanent damage to the device. Exposure to any Absolute
Note 12:
For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is Maximum Rating condition for extended periods may affect device the offset voltage measured from –0.5LSB when the output code flickers reliability and lifetime. between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale
Note 2:
All voltage values are with respect to ground. error for these SoftSpan ranges is the worst-case deviation of the first
Note 3:
V and last code transitions from ideal and includes the effect of offset DDLBYP is the output of an internal voltage regulator, and should only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND, error. For unipolar SoftSpan ranges 5, 4, 1, and 0, zero-scale error is as described in the Pin Functions section. Do not connect this pin to any the offset voltage measured from 0.5LSB when the output code flickers external circuitry. between 0000 0000 0000 0000 and 0000 0000 0000 0001. Full-scale error
Note 4:
When these pin voltages are taken below V for these SoftSpan ranges is the worst-case deviation of the last code EE or above VCC, they will be clamped by internal diodes. This product can handle input currents transition from ideal and includes the effect of offset error. of up to 100mA below V
Note 13:
All specifications in dB are referred to a full-scale input in the EE or above VCC without latch-up.
Note 5:
When these pin voltages are taken below ground or above V relevant SoftSpan input range, except for crosstalk, which is referred to DD or OV the crosstalk injection signal amplitude. DD, they will be clamped by internal diodes. This product can handle currents of up to 100mA below ground or above V
Note 14:
Temperature coefficient is calculated by dividing the maximum DD or OVDD without latch-up. change in output voltage by the specified temperature range.
Note 6:
–16.5V ≤ V
Note 15:
When REFBUF is overdriven, the internal reference buffer must EE ≤ 0V, 0V ≤ VCC ≤ 38V, 10V ≤ (VCC – VEE) ≤ 38V, V be disabled by setting REFIN = 0V. DD = 5V, unless otherwise specified.
Note 7:
Recommended operating conditions.
Note 16:
IREFBUF varies proportionally with sample rate.
Note 8:
Refer to Absolute Maximum Ratings section for pin voltage limits
Note 17:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V, related to device reliability. and OVDD = 5.25V.
Note 9:
V
Note 18:
A t CC = 15V, VEE = –15V, VDD = 5V, OVDD = 2.5V, fSMPL = 1Msps, SCKI period of 10ns minimum allows a shift clock frequency of internal reference and buffer, true bipolar input signal drive in bipolar up to 100MHz for rising edge capture. SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless
Note 19:
VICM = 1.2V, VID = 350mV for LVDS differential input pairs. otherwise specified.
Note 10:
Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
CMOS Timing
0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 233516 F01a 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
LVDS Timing (Differential)
+200mV tWIDTH –200mV t tDELAY 0V 0V DELAY 233516 F01b +200mV +200mV –200mV –200mV
Figure 1. Voltage Levels for Timing Specifications
233516f 8 For more information www.linear.com/LTC2335-16 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Configuration Tables Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Typical Application Related Parts
aDc TiMing characTerisTics Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 11:
Guaranteed by design, not subject to test. may cause permanent damage to the device. Exposure to any Absolute
Note 12:
For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is Maximum Rating condition for extended periods may affect device the offset voltage measured from –0.5LSB when the output code flickers reliability and lifetime. between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale
Note 2:
All voltage values are with respect to ground. error for these SoftSpan ranges is the worst-case deviation of the first
Note 3:
V and last code transitions from ideal and includes the effect of offset DDLBYP is the output of an internal voltage regulator, and should only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND, error. For unipolar SoftSpan ranges 5, 4, 1, and 0, zero-scale error is as described in the Pin Functions section. Do not connect this pin to any the offset voltage measured from 0.5LSB when the output code flickers external circuitry. between 0000 0000 0000 0000 and 0000 0000 0000 0001. Full-scale error
Note 4:
When these pin voltages are taken below V for these SoftSpan ranges is the worst-case deviation of the last code EE or above VCC, they will be clamped by internal diodes. This product can handle input currents transition from ideal and includes the effect of offset error. of up to 100mA below V
Note 13:
All specifications in dB are referred to a full-scale input in the EE or above VCC without latch-up.
Note 5:
When these pin voltages are taken below ground or above V relevant SoftSpan input range, except for crosstalk, which is referred to DD or OV the crosstalk injection signal amplitude. DD, they will be clamped by internal diodes. This product can handle currents of up to 100mA below ground or above V
Note 14:
Temperature coefficient is calculated by dividing the maximum DD or OVDD without latch-up. change in output voltage by the specified temperature range.
Note 6:
–16.5V ≤ V
Note 15:
When REFBUF is overdriven, the internal reference buffer must EE ≤ 0V, 0V ≤ VCC ≤ 38V, 10V ≤ (VCC – VEE) ≤ 38V, V be disabled by setting REFIN = 0V. DD = 5V, unless otherwise specified.
Note 7:
Recommended operating conditions.
Note 16:
IREFBUF varies proportionally with sample rate.
Note 8:
Refer to Absolute Maximum Ratings section for pin voltage limits
Note 17:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V, related to device reliability. and OVDD = 5.25V.
Note 9:
V
Note 18:
A t CC = 15V, VEE = –15V, VDD = 5V, OVDD = 2.5V, fSMPL = 1Msps, SCKI period of 10ns minimum allows a shift clock frequency of internal reference and buffer, true bipolar input signal drive in bipolar up to 100MHz for rising edge capture. SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless
Note 19:
VICM = 1.2V, VID = 350mV for LVDS differential input pairs. otherwise specified.
Note 10:
Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
CMOS Timing
0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 233516 F01a 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
LVDS Timing (Differential)
+200mV tWIDTH –200mV t tDELAY 0V 0V DELAY 233516 F01b +200mV +200mV –200mV –200mV
Figure 1. Voltage Levels for Timing Specifications
233516f 8 For more information www.linear.com/LTC2335-16 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Configuration Tables Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Typical Application Related Parts
