Datasheet LTC2337-18 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 18-Bit, 500ksps, ±10.24V True Bipolar, Fully Differential Input ADC with 100dB SNR |
| Pages / Page | 26 / 8 — PIN FUNCTIONS VDDLBYP (Pin 1):. CHAIN (Pin 10):. DD (Pin 2):. GND (Pins … |
| File Format / Size | PDF / 749 Kb |
| Document Language | English |
PIN FUNCTIONS VDDLBYP (Pin 1):. CHAIN (Pin 10):. DD (Pin 2):. GND (Pins 3, 6 and 16):. BUSY (Pin 11):. IN+, IN– (Pins 4, 5):
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Text Version of Document
LTC2337-18
PIN FUNCTIONS VDDLBYP (Pin 1):
2.5V Supply Bypass Pin. The voltage
CHAIN (Pin 10):
Chain Mode Selector Pin. When low, on this pin is generated via an onboard regulator off of the LTC2337-18 operates in normal mode and the VDD. This pin must be bypassed with a 2.2μF ceramic RDL/SDI input pin functions to enable or disable SDO. capacitor to GND. When high, the LTC2337-18 operates in chain mode and the
V
RDL/SDI pin functions as SDI, the daisy-chain serial data
DD (Pin 2):
5V Power Supply. The range of VDD is 4.75V to 5.25V. Bypass V input. Logic levels are determined by OVDD. DD to GND with a 10µF ceramic capacitor.
GND (Pins 3, 6 and 16):
Ground.
BUSY (Pin 11):
BUSY Indicator. Goes high at the start of a new conversion and returns low when the conversion
IN+, IN– (Pins 4, 5):
Positive and Negative Differential has finished. Logic levels are determined by OVDD. Analog Inputs. Typical input range ±10.24V.
RDL/SDI (Pin 12):
When CHAIN is low, the part is in nor-
REFBUF (Pin 7):
Reference Buffer Output. An onboard mal mode and the pin is treated as a bus enabling input. buffer nominally outputs 4.096V to this pin. This pin is When CHAIN is high, the part is in chain mode and the referred to GND and should be decoupled closely to the pin pin is treated as a serial data input pin where data from with a 47μF ceramic capacitor. The internal buffer driving another ADC in the daisy chain is input. Logic levels are this pin may be disabled by grounding its input at REFIN. determined by OVDD. Once the buffer is disabled, an external reference may overdrive this pin in the range of 2.5V to 5V. A resistive
SCK (Pin 13):
Serial Data Clock Input. When SDO is enabled, load greater than 500kΩ can be placed on the reference the conversion result or daisy-chain data from another buffer output. ADC is shifted out on the rising edges of this clock MSB first. Logic levels are determined by OVDD.
REFIN (Pin 8):
Reference Output/Reference Buffer Input. An onboard bandgap reference nominally outputs 2.048V
SDO (Pin 14):
Serial Data Output. The conversion result or at this pin. Bypass this pin with a 100nF ceramic capacitor daisy-chain data is output on this pin on each rising edge to GND to limit the reference output noise. If more accu- of SCK MSB first. The output data is in 2’s complement racy is desired, this pin may be overdriven by an external format. Logic levels are determined by OVDD. reference in the range of 1.25V to 2.4V.
OVDD (Pin 15):
I/O Interface Digital Power. The range of
CNV (Pin 9):
Convert Input. A rising edge on this input OVDD is 1.71V to 5.25V. This supply is nominally set to powers up the part and initiates a new conversion. Logic the same supply as the host interface (1.8V, 2.5V, 3.3V, levels are determined by OV or 5V). Bypass OVDD to GND with a 0.1μF capacitor. DD. 233718fa 8 For more information www.linear.com/LTC2337-18 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS VDDLBYP (Pin 1):
2.5V Supply Bypass Pin. The voltage
CHAIN (Pin 10):
Chain Mode Selector Pin. When low, on this pin is generated via an onboard regulator off of the LTC2337-18 operates in normal mode and the VDD. This pin must be bypassed with a 2.2μF ceramic RDL/SDI input pin functions to enable or disable SDO. capacitor to GND. When high, the LTC2337-18 operates in chain mode and the
V
RDL/SDI pin functions as SDI, the daisy-chain serial data
DD (Pin 2):
5V Power Supply. The range of VDD is 4.75V to 5.25V. Bypass V input. Logic levels are determined by OVDD. DD to GND with a 10µF ceramic capacitor.
GND (Pins 3, 6 and 16):
Ground.
BUSY (Pin 11):
BUSY Indicator. Goes high at the start of a new conversion and returns low when the conversion
IN+, IN– (Pins 4, 5):
Positive and Negative Differential has finished. Logic levels are determined by OVDD. Analog Inputs. Typical input range ±10.24V.
RDL/SDI (Pin 12):
When CHAIN is low, the part is in nor-
REFBUF (Pin 7):
Reference Buffer Output. An onboard mal mode and the pin is treated as a bus enabling input. buffer nominally outputs 4.096V to this pin. This pin is When CHAIN is high, the part is in chain mode and the referred to GND and should be decoupled closely to the pin pin is treated as a serial data input pin where data from with a 47μF ceramic capacitor. The internal buffer driving another ADC in the daisy chain is input. Logic levels are this pin may be disabled by grounding its input at REFIN. determined by OVDD. Once the buffer is disabled, an external reference may overdrive this pin in the range of 2.5V to 5V. A resistive
SCK (Pin 13):
Serial Data Clock Input. When SDO is enabled, load greater than 500kΩ can be placed on the reference the conversion result or daisy-chain data from another buffer output. ADC is shifted out on the rising edges of this clock MSB first. Logic levels are determined by OVDD.
REFIN (Pin 8):
Reference Output/Reference Buffer Input. An onboard bandgap reference nominally outputs 2.048V
SDO (Pin 14):
Serial Data Output. The conversion result or at this pin. Bypass this pin with a 100nF ceramic capacitor daisy-chain data is output on this pin on each rising edge to GND to limit the reference output noise. If more accu- of SCK MSB first. The output data is in 2’s complement racy is desired, this pin may be overdriven by an external format. Logic levels are determined by OVDD. reference in the range of 1.25V to 2.4V.
OVDD (Pin 15):
I/O Interface Digital Power. The range of
CNV (Pin 9):
Convert Input. A rising edge on this input OVDD is 1.71V to 5.25V. This supply is nominally set to powers up the part and initiates a new conversion. Logic the same supply as the host interface (1.8V, 2.5V, 3.3V, levels are determined by OV or 5V). Bypass OVDD to GND with a 0.1μF capacitor. DD. 233718fa 8 For more information www.linear.com/LTC2337-18 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Revision History Typical Application Related Parts
