Datasheet LTC2351-12 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 6 Channel, 12-Bit, 1.5Msps Simultaneous Sampling ADC with Shutdown |
| Pages / Page | 20 / 5 — TIMING CHARACTERISTICS. The. denotes the specifi cations which apply over … |
| File Format / Size | PDF / 235 Kb |
| Document Language | English |
TIMING CHARACTERISTICS. The. denotes the specifi cations which apply over the full operating temperature
Model Line for this Datasheet
Text Version of Document
LTC2351-12
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t9 SCK↑ to Hi-Z at SDO (Notes 6, 12) 6 ns t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns t11 VREF Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 10:
If less than 3ns is allowed, the output data will appear one may cause permanent damage to the device. Exposure to any Absolute clock cycle later. It is best for CONV to rise half a clock before SCK, when Maximum Rating condition for extended periods may affect device running the clock at rated speed. reliabilty and lifetime.
Note 11:
Not the same as aperture delay. Aperture delay (1ns) is the
Note 2:
All voltage values are with respect to ground GND. difference between the 2.2ns delay through the sample-and-hold and the
Note 3:
When these pins are taken below GND or above V 1.2ns CONV to Hold mode delay. DD, they will be clamped by internal diodes. This product can handle input currents greater
Note 12:
The rising edge of SCK is guaranteed to catch the data coming than 100mA below GND or greater than VDD without latchup. out into a storage latch.
Note 4:
Offset and range specifi cations apply for a single-ended CH0+
Note 13:
The time period for acquiring the input signal is started by the – CH5+ input with CH0– – CH5– grounded and using the internal 2.5V 96th rising clock and it is ended by the rising edge of CONV. reference.
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep
Note 5:
Integral linearity is tested with an external 2.55V reference and is mode with one or more cycles at SCK and a 10μF capacitive load. defi ned as the deviation of a code from the straight line passing through
Note 15:
The full power bandwidth is the frequency where the output code the actual endpoints of a transfer curve. The deviation is measured from swing drops by 3dB with a 2.5VP-P input sine wave. the center of quantization band. Linearity is tested for CH0 only.
Note 16:
Maximum clock period guarantees analog performance during
Note 6:
Guaranteed by design, not subject to test. conversion. Output data can be read with an arbitrarily long clock period.
Note 7:
Recommended operating conditions.
Note 17:
The conversion process takes 16 clocks for each channel that is
Note 8:
The analog input range is defi ned for the voltage difference enabled, up to 96 clocks for all 6 channels. between CHx+ and CHx–, x = 0 to 5.
Note 9:
The absolute voltage at CHx+ and CHx– must be within this range. 235112fa 5
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t9 SCK↑ to Hi-Z at SDO (Notes 6, 12) 6 ns t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns t11 VREF Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 10:
If less than 3ns is allowed, the output data will appear one may cause permanent damage to the device. Exposure to any Absolute clock cycle later. It is best for CONV to rise half a clock before SCK, when Maximum Rating condition for extended periods may affect device running the clock at rated speed. reliabilty and lifetime.
Note 11:
Not the same as aperture delay. Aperture delay (1ns) is the
Note 2:
All voltage values are with respect to ground GND. difference between the 2.2ns delay through the sample-and-hold and the
Note 3:
When these pins are taken below GND or above V 1.2ns CONV to Hold mode delay. DD, they will be clamped by internal diodes. This product can handle input currents greater
Note 12:
The rising edge of SCK is guaranteed to catch the data coming than 100mA below GND or greater than VDD without latchup. out into a storage latch.
Note 4:
Offset and range specifi cations apply for a single-ended CH0+
Note 13:
The time period for acquiring the input signal is started by the – CH5+ input with CH0– – CH5– grounded and using the internal 2.5V 96th rising clock and it is ended by the rising edge of CONV. reference.
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep
Note 5:
Integral linearity is tested with an external 2.55V reference and is mode with one or more cycles at SCK and a 10μF capacitive load. defi ned as the deviation of a code from the straight line passing through
Note 15:
The full power bandwidth is the frequency where the output code the actual endpoints of a transfer curve. The deviation is measured from swing drops by 3dB with a 2.5VP-P input sine wave. the center of quantization band. Linearity is tested for CH0 only.
Note 16:
Maximum clock period guarantees analog performance during
Note 6:
Guaranteed by design, not subject to test. conversion. Output data can be read with an arbitrarily long clock period.
Note 7:
Recommended operating conditions.
Note 17:
The conversion process takes 16 clocks for each channel that is
Note 8:
The analog input range is defi ned for the voltage difference enabled, up to 96 clocks for all 6 channels. between CHx+ and CHx–, x = 0 to 5.
Note 9:
The absolute voltage at CHx+ and CHx– must be within this range. 235112fa 5
