Datasheet LTC2351-14 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 6 Channel, 14-Bit, 1.5Msps Simultaneous Sampling ADC with Shutdown |
| Pages / Page | 20 / 5 — TIMING CHARACTERISTICS. Note 5:. Note 12:. Note 13:. Note 6:. Note 14:. … |
| File Format / Size | PDF / 244 Kb |
| Document Language | English |
TIMING CHARACTERISTICS. Note 5:. Note 12:. Note 13:. Note 6:. Note 14:. Note 7:. Note 8:. Note 15:. Note 9:. Note 16:. Note 10:. Note 17:
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LTC2351-14
TIMING CHARACTERISTICS Note 5:
Integral linearity is tested with an external 2.55V reference and is
Note 12:
The rising edge of SCK is guaranteed to catch the data coming defi ned as the deviation of a code from the straight line passing through out into a storage latch. the actual endpoints of a transfer curve. The deviation is measured from
Note 13:
The time period for acquiring the input signal is started by the the center of quantization band. Linearity is tested for CH0 only. 96th rising clock and it is ended by the rising edge of CONV.
Note 6:
Guaranteed by design, not subject to test.
Note 14:
The internal reference settles in 2ms after it wakes up from sleep
Note 7:
Recommended operating conditions. mode with one or more cycles at SCK and a 10μF capacitive load.
Note 8:
The analog input range is defi ned for the voltage difference
Note 15:
The full power bandwidth is the frequency where the output code between CHx+ and CHx–, x = 0–5. swing drops by 3dB with a 2.5VP-P input sine wave.
Note 9:
The absolute voltage at CHx+ and CHx– must be within this range.
Note 16:
Maximum clock period guarantees analog performance during
Note 10:
If less than 3ns is allowed, the output data will appear one conversion. Output data can be read with an arbitrarily long clock period. clock cycle later. It is best for CONV to rise half a clock before SCK, when
Note 17:
The conversion process takes 16 clocks for each channel that is running the clock at rated speed. enabled, up to 96 clocks for all six channels.
Note 11:
Not the same as aperture delay. Aperture delay (1ns) is the difference between the 2.2ns delay through the sample-and-hold and the 1.2ns CONV to Hold mode delay.
TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, TA = 25°C THD, 2nd and 3rd THD, 2nd and 3rd SINAD vs Input Frequency vs Input Frequency vs Input Frequency
77 –50 –50 UNIPOLAR SINGLE-ENDED BIPOLAR SINGLE-ENDED –56 –56 74 –62 –62 THD THD 71 –68 –68 2nd 2nd 68 –74 –74 –80 –80 65 SINAD (dB) –86 3rd –86 THD, 2nd, 3rd (dB) THD, 2nd, 3rd (dB) 62 –92 –92 3rd –98 –98 59 –104 –104 56 –110 –110 0.1 1 10 0.1 1 10 0.1 1 10 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) 235114 G01 235114 G02 235114 G03
SFDR vs Input Frequency SNR vs Input Frequency
92 77 86 74 80 71 74 68 68 SFDR (dB) SNR (dB) 65 62 62 56 59 50 56 0.1 1 10 0.1 1 10 FREQUENCY (MHz) FREQUENCY (MHz) 235114 G04 235114 G05 235114fb 5
TIMING CHARACTERISTICS Note 5:
Integral linearity is tested with an external 2.55V reference and is
Note 12:
The rising edge of SCK is guaranteed to catch the data coming defi ned as the deviation of a code from the straight line passing through out into a storage latch. the actual endpoints of a transfer curve. The deviation is measured from
Note 13:
The time period for acquiring the input signal is started by the the center of quantization band. Linearity is tested for CH0 only. 96th rising clock and it is ended by the rising edge of CONV.
Note 6:
Guaranteed by design, not subject to test.
Note 14:
The internal reference settles in 2ms after it wakes up from sleep
Note 7:
Recommended operating conditions. mode with one or more cycles at SCK and a 10μF capacitive load.
Note 8:
The analog input range is defi ned for the voltage difference
Note 15:
The full power bandwidth is the frequency where the output code between CHx+ and CHx–, x = 0–5. swing drops by 3dB with a 2.5VP-P input sine wave.
Note 9:
The absolute voltage at CHx+ and CHx– must be within this range.
Note 16:
Maximum clock period guarantees analog performance during
Note 10:
If less than 3ns is allowed, the output data will appear one conversion. Output data can be read with an arbitrarily long clock period. clock cycle later. It is best for CONV to rise half a clock before SCK, when
Note 17:
The conversion process takes 16 clocks for each channel that is running the clock at rated speed. enabled, up to 96 clocks for all six channels.
Note 11:
Not the same as aperture delay. Aperture delay (1ns) is the difference between the 2.2ns delay through the sample-and-hold and the 1.2ns CONV to Hold mode delay.
TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, TA = 25°C THD, 2nd and 3rd THD, 2nd and 3rd SINAD vs Input Frequency vs Input Frequency vs Input Frequency
77 –50 –50 UNIPOLAR SINGLE-ENDED BIPOLAR SINGLE-ENDED –56 –56 74 –62 –62 THD THD 71 –68 –68 2nd 2nd 68 –74 –74 –80 –80 65 SINAD (dB) –86 3rd –86 THD, 2nd, 3rd (dB) THD, 2nd, 3rd (dB) 62 –92 –92 3rd –98 –98 59 –104 –104 56 –110 –110 0.1 1 10 0.1 1 10 0.1 1 10 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) 235114 G01 235114 G02 235114 G03
SFDR vs Input Frequency SNR vs Input Frequency
92 77 86 74 80 71 74 68 68 SFDR (dB) SNR (dB) 65 62 62 56 59 50 56 0.1 1 10 0.1 1 10 FREQUENCY (MHz) FREQUENCY (MHz) 235114 G04 235114 G05 235114fb 5
