Datasheet LTC2380-16 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 16-Bit, 2Msps, Low Power SAR ADC with 96.2dB SNR |
| Pages / Page | 26 / 8 — PIN FUNCTIONS CHAIN (Pin 1):. BUSY (Pin 11):. RDL/SDI (Pin 12):. VDD (Pin … |
| File Format / Size | PDF / 694 Kb |
| Document Language | English |
PIN FUNCTIONS CHAIN (Pin 1):. BUSY (Pin 11):. RDL/SDI (Pin 12):. VDD (Pin 2):. GND (Pins 3, 6, 10 and 16):. SCK (Pin 13):
Model Line for this Datasheet
- LTC2380CDE-16#PBF LTC2380CDE-16#PBF LTC2380CDE-16#TRPBF LTC2380CDE-16#TRPBF LTC2380CMS-16#PBF LTC2380CMS-16#PBF LTC2380CMS-16#TRPBF LTC2380CMS-16#TRPBF LTC2380HMS-16#PBF LTC2380HMS-16#PBF LTC2380HMS-16#TRPBF LTC2380HMS-16#TRPBF LTC2380IDE-16#PBF LTC2380IDE-16#PBF LTC2380IDE-16#TRPBF LTC2380IDE-16#TRPBF LTC2380IMS-16#PBF LTC2380IMS-16#PBF LTC2380IMS-16#TRPBF LTC2380IMS-16#TRPBF
Text Version of Document
LTC2380-16
PIN FUNCTIONS CHAIN (Pin 1):
Chain Mode Selector Pin. When low, the
BUSY (Pin 11):
BUSY Indicator. Goes high at the start of LTC2380-16 operates in normal mode and the RDL/SDI a new conversion and returns low when the conversion input pin functions to enable or disable SDO. When high, has finished. Logic levels are determined by 0VDD. the LTC2380-16 operates in chain mode and the RDL/SDI
RDL/SDI (Pin 12):
When CHAIN is low, the part is in nor- pin functions as SDI, the daisy chain serial data input. mal mode and the pin is treated as a bus enabling input. Logic levels are determined by 0VDD. When CHAIN is high, the part is in chain mode and the
VDD (Pin 2):
2.5V Power Supply. The range of VDD is pin is treated as a serial data input pin where data from 2.375V to 2.625V. Bypass VDD to GND with a 10µF ceramic another ADC in the daisy chain is input. Logic levels are capacitor. determined by 0VDD.
GND (Pins 3, 6, 10 and 16):
Ground.
SCK (Pin 13):
Serial Data Clock Input. When SDO is enabled,
IN+, IN– (Pins 4, 5):
Positive and Negative Differential the conversion result or daisy chain data from another Analog Inputs. ADC is shifted out on the rising edges of this clock MSB first. Logic levels are determined by 0VDD.
REF (Pin 7):
Reference Input. The range of REF is 2.5V to 5.1V. This pin is referred to the GND pin and should be
SDO (Pin 14):
Serial Data Output. The conversion result or decoupled closely to the pin with a 47µF ceramic capacitor daisy chain data is output on this pin on each rising edge (X5R, 0805 size). of SCK MSB first. The output data is in 2’s complement format. Logic levels are determined by 0VDD.
REF/DGC (Pin 8):
When tied to REF, digital gain compression is disabled and the LTC2380-16 defines full-scale accord-
OVDD (Pin 15):
I/O Interface Digital Power. The range of ing to the ±V OVDD is 1.71V to 5.25V. This supply is nominally set to REF analog input range. When tied to GND, digital gain compression is enabled and the LTC2380-16 the same supply as the host interface (1.8V, 2.5V, 3.3V, defines full-scale with inputs that swing between 10% and or 5V). Bypass OVDD to GND with a 0.1µF capacitor. 90% of the ±VREF analog input range.
GND (Exposed Pad Pin 17 – DFN Package Only):
Ground.
CNV (Pin 9):
Convert Input. A rising edge on this input Exposed pad must be soldered directly to the ground plane. powers up the part and initiates a new conversion. Logic levels are determined by 0VDD.
FUNCTIONAL BLOCK DIAGRAM
VDD = 2.5V REF = 5V OVDD = 1.8V to 5V LTC2380-16 CHAIN IN+ + SDO SPI RDL/SDI 16-BIT SAMPLING ADC PORT SCK IN– – CNV BUSY CONTROL LOGIC REF/DGC GND 238016 BD01 238016fb 8 For more information www.linear.com/LTC2380-16 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Typical Application Related Parts
PIN FUNCTIONS CHAIN (Pin 1):
Chain Mode Selector Pin. When low, the
BUSY (Pin 11):
BUSY Indicator. Goes high at the start of LTC2380-16 operates in normal mode and the RDL/SDI a new conversion and returns low when the conversion input pin functions to enable or disable SDO. When high, has finished. Logic levels are determined by 0VDD. the LTC2380-16 operates in chain mode and the RDL/SDI
RDL/SDI (Pin 12):
When CHAIN is low, the part is in nor- pin functions as SDI, the daisy chain serial data input. mal mode and the pin is treated as a bus enabling input. Logic levels are determined by 0VDD. When CHAIN is high, the part is in chain mode and the
VDD (Pin 2):
2.5V Power Supply. The range of VDD is pin is treated as a serial data input pin where data from 2.375V to 2.625V. Bypass VDD to GND with a 10µF ceramic another ADC in the daisy chain is input. Logic levels are capacitor. determined by 0VDD.
GND (Pins 3, 6, 10 and 16):
Ground.
SCK (Pin 13):
Serial Data Clock Input. When SDO is enabled,
IN+, IN– (Pins 4, 5):
Positive and Negative Differential the conversion result or daisy chain data from another Analog Inputs. ADC is shifted out on the rising edges of this clock MSB first. Logic levels are determined by 0VDD.
REF (Pin 7):
Reference Input. The range of REF is 2.5V to 5.1V. This pin is referred to the GND pin and should be
SDO (Pin 14):
Serial Data Output. The conversion result or decoupled closely to the pin with a 47µF ceramic capacitor daisy chain data is output on this pin on each rising edge (X5R, 0805 size). of SCK MSB first. The output data is in 2’s complement format. Logic levels are determined by 0VDD.
REF/DGC (Pin 8):
When tied to REF, digital gain compression is disabled and the LTC2380-16 defines full-scale accord-
OVDD (Pin 15):
I/O Interface Digital Power. The range of ing to the ±V OVDD is 1.71V to 5.25V. This supply is nominally set to REF analog input range. When tied to GND, digital gain compression is enabled and the LTC2380-16 the same supply as the host interface (1.8V, 2.5V, 3.3V, defines full-scale with inputs that swing between 10% and or 5V). Bypass OVDD to GND with a 0.1µF capacitor. 90% of the ±VREF analog input range.
GND (Exposed Pad Pin 17 – DFN Package Only):
Ground.
CNV (Pin 9):
Convert Input. A rising edge on this input Exposed pad must be soldered directly to the ground plane. powers up the part and initiates a new conversion. Logic levels are determined by 0VDD.
FUNCTIONAL BLOCK DIAGRAM
VDD = 2.5V REF = 5V OVDD = 1.8V to 5V LTC2380-16 CHAIN IN+ + SDO SPI RDL/SDI 16-BIT SAMPLING ADC PORT SCK IN– – CNV BUSY CONTROL LOGIC REF/DGC GND 238016 BD01 238016fb 8 For more information www.linear.com/LTC2380-16 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Typical Application Related Parts
