Datasheet LTC2386-18 (Analog Devices) - 8

LTC2386-18
Typical perForMance characTerisTics TA = 25°C, VDD = 5V, VDDL = 2.5V, OVDD = 2.5V, REFIN = 2.048V, fSMPL = 10Msps, unless otherwise noted. Analog Input Current Internal Reference Output Supply Current vs Sample Rate vs Differential Input V Differential Input V oltage oltage vs Temperature
30 0.75 2.050 fSMPL = 10Msps THREE TYPICAL UNITS IN– 25 0.50 20 0.25 2.049 IVDDL IVDD 15 0 IOVDD Y CURRENT (mA) 10 –0.25 2.048 SUPPL IN+ REFERENCE OUTPUT (V) ANALOG INPUT CURRENT (mA) 5 –0.50 0 –0.75 2.047 0 2.5 5 7.5 10 –4.096 –2.048 0 2.048 4.096 –40 –20 0 20 40 60 80 SAMPLE RATE (MHz) DIFFERENTIAL INPUT (V) TEMPERATURE (°C) 238618 G18 238618 G19 238618 G20
pin FuncTions GND (Pins 1, 4, 10, 21, 26, 29 ):
Ground. Connect to a can be applied to REFIN if a more accurate reference is solid ground plane in the PCB underneath the ADC. required. For increased filtering of reference noise, bypass
IN+, IN– (Pins 2, 3):
Positive and Negative Differential this pin to GND using a 0.1µF or larger ceramic capacitor. Analog Inputs. The inputs must be driven differentially If the internal reference buffer is not used, tie REFIN to and 180° out of phase, with a common mode voltage of GND to power down the buffer and connect an external 2.048V. The differential input range is ±4.096V (each input buffered reference to REFBUF. pin swings from 0V to 4.096V.)
VDD (Pins 11, 12):
5V Analog Power Supply. The range
REFGND (Pins 5, 6):
Reference Ground. The two pins of VDD is 4.75V to 5.25V. The two pins should be shorted should be shorted together and connected to the refer- together and bypassed to GND with 0.1μF and 10μF ce- ence bypass capacitor with a short, wide trace. In ad- ramic capacitors. dition, connect the pins to the exposed pad (Pin 33). A
PD (Pin 13):
Digital input that enables power-down mode. suggested layout is shown in the ADC Reference section When PD is low, the LTC2386 enters power-down mode, of the data sheet. and all circuitry (including the LVDS interface) is shut
REFBUF (Pins 7, 8):
Internal Reference Buffer Output. down. When PD is high, the part operates normally. Logic The output voltage of the internal 2× gain reference buffer, levels are determined by OVDD. nominally 4.096V, is provided on this pin. The two pins
TESTPAT (Pin 14):
Digital input that forces the LVDS data should be shorted together and bypassed to REFGND with outputs to be a test pattern. When TESTPAT is high, the a 10µF (X7R, 0805 size) ceramic capacitor. If the internal digital outputs are a test pattern. When TESTPAT is low, buffer is not required, tie REFIN to GND to power down the digital outputs are the ADC conversion result. Logic the buffer and connect an external 4.096V reference to levels are determined by OVDD. REFBUF.
DB–/DB+, DA–/DA+ (Pins 15/16, 17/18):
Serial LVDS
REFIN (Pin 9):
Internal Reference Output/Reference Buffer Data Outputs. In one-lane output mode, DB–/DB+ are not Input. The output voltage of the internal reference, nomi- used and their LVDS driver is disabled to reduce power nally 2.048V, is output on this pin. An external reference consumption. 238618f 8 For more information www.linear.com/LTC2386-18 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Typical Application Related Parts