Datasheet LTC2404, LTC2408 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 4-/8-Channel 24-Bit µPower No Latency ∆∑TM ADCs |
| Pages / Page | 36 / 9 — TYPICAL PERFOR A CE CHARACTERISTICS. Resolution vs Maximum. INL vs … |
| File Format / Size | PDF / 374 Kb |
| Document Language | English |
TYPICAL PERFOR A CE CHARACTERISTICS. Resolution vs Maximum. INL vs Maximum Output Rate. Output Rate. PIN FUNCTIONS
Model Line for this Datasheet
Text Version of Document
LTC2404/LTC2408
W U TYPICAL PERFOR A CE CHARACTERISTICS Resolution vs Maximum INL vs Maximum Output Rate Output Rate
24 24 VCC = 5V FO = EXTERNAL V (20480 × MAXIMUM 22 REF = 5V 22 F0 = EXTERNAL OUTPUT RATE) (20480 × MAXIMUM T 20 20 A = 25°C OUTPUT RATE) TA = 90°C 18 18 VCC = VREF = 5V 16 16 INL (BITS) TA = 25°C VCC = VREF = 3V 14 14 TA = 90°C RESOLUTION (BITS)* 12 12 10 10 LOG(V *RESOLUTION = REF/RMS NOISE) LOG (2) 8 8 0 5 10 15 20 25 30 35 40 45 50 55 60 0 5 10 15 20 25 30 35 40 45 50 55 60 MAXIMUM OUTPUT RATE (Hz) MAXIMUM OUTPUT RATE (Hz) 24048 G27 24048 G28
U U U PIN FUNCTIONS GND (Pins 1, 5, 6, 16, 18, 22, 27, 28):
Ground. Should be
CH5 (Pin 14):
Analog Multiplexer Input. No connect on the connected directly to a ground plane through a minimum LTC2404. length trace or it should be the single-point-ground in a
CH6 (Pin 15):
Analog Multiplexer Input. No connect on the single point grounding system. LTC2404.
VCC (Pins 2, 8):
Positive Supply Voltage. 2.7V ≤ VCC ≤
CH7 (Pin 17):
Analog Multiplexer Input. No connect on the 5.5V. Bypass to GND with a 10µF tantalum capacitor in LTC2404. parallel with 0.1µF ceramic capacitor as close to the part as possible.
CLK (Pin 19):
Shift Clock for Data In. This clock synchro- nizes the serial data transfer into the MUX. For normal
VREF (Pin 3):
Reference Input. The reference voltage range operation, drive this pin in parallel with SCK. is 0.1V to VCC.
CSMUX (Pin 20):
MUX Chip Select Input. A logic high on
ADCIN (Pin 4):
Analog Input. The input voltage range is this input allows the MUX to receive a channel address. A – 0.125 • VREF to 1.125 • VREF. For VREF > 2.5V the input logic low enables the selected MUX channel and connects voltage range may be limited by the pin absolute maxi- it to the MUXOUT pin for A/D conversion. For normal mum rating of – 0.3V to VCC + 0.3V. operation, drive this pin in parallel with CSADC.
MUXOUT (Pin 7):
MUX Output. This pin is the output of the
D
multiplexer. Tie to ADCIN for normal operation.
IN (Pin 21):
Digital Data Input. The multiplexer address is shifted into this input on the last four rising CLK edges
CH0 (Pin 9):
Analog Multiplexer Input. before CSMUX goes low.
CH1 (Pin 10):
Analog Multiplexer Input.
CSADC (Pin 23):
ADC Chip Select Input. A low on this pin enables the SDO digital output and following each conver-
CH2 (Pin 11):
Analog Multiplexer Input. sion, the ADC automatically enters the Sleep mode and
CH3 (Pin 12):
Analog Multiplexer Input. remains in this low power state as long as CSADC is high.
CH4 (Pin 13):
Analog Multiplexer Input. No connect on the A high on this pin also disables the SDO digital output. A LTC2404. low-to-high transition on CSADC during the Data Output 9
W U TYPICAL PERFOR A CE CHARACTERISTICS Resolution vs Maximum INL vs Maximum Output Rate Output Rate
24 24 VCC = 5V FO = EXTERNAL V (20480 × MAXIMUM 22 REF = 5V 22 F0 = EXTERNAL OUTPUT RATE) (20480 × MAXIMUM T 20 20 A = 25°C OUTPUT RATE) TA = 90°C 18 18 VCC = VREF = 5V 16 16 INL (BITS) TA = 25°C VCC = VREF = 3V 14 14 TA = 90°C RESOLUTION (BITS)* 12 12 10 10 LOG(V *RESOLUTION = REF/RMS NOISE) LOG (2) 8 8 0 5 10 15 20 25 30 35 40 45 50 55 60 0 5 10 15 20 25 30 35 40 45 50 55 60 MAXIMUM OUTPUT RATE (Hz) MAXIMUM OUTPUT RATE (Hz) 24048 G27 24048 G28
U U U PIN FUNCTIONS GND (Pins 1, 5, 6, 16, 18, 22, 27, 28):
Ground. Should be
CH5 (Pin 14):
Analog Multiplexer Input. No connect on the connected directly to a ground plane through a minimum LTC2404. length trace or it should be the single-point-ground in a
CH6 (Pin 15):
Analog Multiplexer Input. No connect on the single point grounding system. LTC2404.
VCC (Pins 2, 8):
Positive Supply Voltage. 2.7V ≤ VCC ≤
CH7 (Pin 17):
Analog Multiplexer Input. No connect on the 5.5V. Bypass to GND with a 10µF tantalum capacitor in LTC2404. parallel with 0.1µF ceramic capacitor as close to the part as possible.
CLK (Pin 19):
Shift Clock for Data In. This clock synchro- nizes the serial data transfer into the MUX. For normal
VREF (Pin 3):
Reference Input. The reference voltage range operation, drive this pin in parallel with SCK. is 0.1V to VCC.
CSMUX (Pin 20):
MUX Chip Select Input. A logic high on
ADCIN (Pin 4):
Analog Input. The input voltage range is this input allows the MUX to receive a channel address. A – 0.125 • VREF to 1.125 • VREF. For VREF > 2.5V the input logic low enables the selected MUX channel and connects voltage range may be limited by the pin absolute maxi- it to the MUXOUT pin for A/D conversion. For normal mum rating of – 0.3V to VCC + 0.3V. operation, drive this pin in parallel with CSADC.
MUXOUT (Pin 7):
MUX Output. This pin is the output of the
D
multiplexer. Tie to ADCIN for normal operation.
IN (Pin 21):
Digital Data Input. The multiplexer address is shifted into this input on the last four rising CLK edges
CH0 (Pin 9):
Analog Multiplexer Input. before CSMUX goes low.
CH1 (Pin 10):
Analog Multiplexer Input.
CSADC (Pin 23):
ADC Chip Select Input. A low on this pin enables the SDO digital output and following each conver-
CH2 (Pin 11):
Analog Multiplexer Input. sion, the ADC automatically enters the Sleep mode and
CH3 (Pin 12):
Analog Multiplexer Input. remains in this low power state as long as CSADC is high.
CH4 (Pin 13):
Analog Multiplexer Input. No connect on the A high on this pin also disables the SDO digital output. A LTC2404. low-to-high transition on CSADC during the Data Output 9
