Datasheet LTC2420 (Analog Devices) - 8

LTC2420
W U TYPICAL PERFOR A CE CHARACTERISTICS INL vs Output Rate INL vs Output Rate Resolution vs Output Rate
20 20 24 V V V T CC = 5V CC = 3V CC = 5V A = 25°C V V V T REF = 5V REF = 2.5V REF = 5V A = 90°C F F f T O = EXTERNAL O = EXTERNAL O = EXTERNAL A = –45°C 18 18 22 16 T 16 A = –45°C T T A = –45°C A = 25°C 20 14 14 RESOLUTION (BITS) T TA = 25°C T TUE RESOLUTION (BITS) A = 90°C TUE RESOLUTION (BITS) A = 90°C 18 12 12 10 10 16 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 0 7.5 25 50 75 100 OUTPUT RATE (Hz) OUTPUT RATE (Hz) OUTPUT RATE (Hz) 2420 G30 2420 G28 2420 G29
U U U PIN FUNCTIONS VCC (Pin 1):
Positive Supply Voltage. Bypass to GND
SDO (Pin 6):
Three-State Digital Output. During the data (Pin␣ 4) with a 10µF tantalum capacitor in parallel with output period this pin is used for serial data output. When 0.1µF ceramic capacitor as close to the part as possible. the chip select CS is HIGH (CS = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep
VREF (Pin 2):
Reference Input. The reference voltage range periods, this pin can be used as a conversion status out- is 0.1V to VCC. put. The conversion status can be observed by pulling CS
VIN (Pin 3):
Analog Input. The input voltage range is LOW. – 0.125 • VREF to 1.125 • VREF. For VREF > 2.5V the input
SCK (Pin 7):
Bidirectional Digital Clock Pin. In Internal voltage range may be limited by the pin absolute maxi- Serial Clock Operation mode, SCK is used as digital output mum rating of – 0.3V to VCC + 0.3V. for the internal serial interface clock during the data output
GND (Pin 4):
Ground. Shared pin for analog ground, period. In External Serial Clock Operation mode, SCK is digital ground, reference ground and signal ground. Should used as digital input for the external serial interface. A be connected directly to a ground plane through a mini- weak internal pull-up is automatically activated in Internal mum length trace or it should be the single-point-ground Serial Clock Operation mode. The Serial Clock mode is in a single point grounding system. determined by the level applied to SCK at power up and the
CS (Pin 5):
Active LOW Digital Input. A LOW on this pin falling edge of CS. enables the SDO digital output and wakes up the ADC.
FO (Pin 8):
Frequency Control Pin. Digital input that Following each conversion, the ADC automatically enters controls the ADC’s notch frequencies and conversion the Sleep mode and remains in this low power state as time. When the FO pin is connected to VCC (FO = VCC), the long as CS is HIGH. A LOW on CS wakes up the ADC. A converter uses its internal oscillator and the digital filter’s LOW-to-HIGH transition on this pin disables the SDO first null is located at 50Hz. When the FO pin is connected digital output. A LOW-to-HIGH transition on CS during the to GND (FO = OV), the converter uses its internal oscillator Data Output transfer aborts the data transfer and starts a and the digital filter first null is located at 60Hz. When FO new conversion. is driven by an external clock signal with a frequency fEOSC, the converter uses this signal as its clock and the digital filter first null is located at a frequency fEOSC/2560. 8