Datasheet LTC2424, LTC2428 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 4-/8-Channel 20-Bit µPower No Latency ∆ΣTM ADCs |
| Pages / Page | 36 / 10 — PIN FUNCTIONS. CSADC (Pin 23):. SCK (Pin 25):. O (Pin 26):. SDO (Pin … |
| File Format / Size | PDF / 431 Kb |
| Document Language | English |
PIN FUNCTIONS. CSADC (Pin 23):. SCK (Pin 25):. O (Pin 26):. SDO (Pin 24):. FU CTIO AL BLOCK DIAGRA. TEST CIRCUITS
Model Line for this Datasheet
Text Version of Document
LTC2424/LTC2428
U U U PIN FUNCTIONS CSADC (Pin 23):
ADC Chip Select Input. A low on this pin
SCK (Pin 25):
Shift Clock for Data Out. This clock synchro- enables the SDO digital output and following each conver- nizes the serial data transfer of the ADC data output. Data sion, the ADC automatically enters the Sleep mode and is shifted out of SDO on the falling edge of SCK. For normal remains in a low power state as long as CSADC is high. If operation, drive this pin in parallel with CLK. CSADC is low during the sleep state, the device draws
F
normal power. A high on this pin also disables the SDO
O (Pin 26):
Digital input which controls the ADC’s notch frequencies and conversion time. When the F digital output. A low-to-high transition on CSADC during O pin is connected to V the Data Output state aborts the data transfer and starts a CC (FO = VCC), the converter uses its internal oscillator and the digital filter first null is located at 50Hz. new conversion. For normal operation, drive this pin in When the F parallel with CSMUX. O pin is connected to GND (FO = OV), the converter uses its internal oscillator and the digital filter
SDO (Pin 24):
Three-State Digital Output. During the data first null is located at 60Hz. When FO is driven by an output period this pin is used for serial data output. When external clock signal with a frequency fEOSC, the converter the chip select CSADC is high (CSADC = VCC), the SDO pin uses this signal as its clock and the digital filter first null is is in a high impedance state. During the Conversion and located at a frequency fEOSC/2560. The resulting output Sleep periods, this pin can be used as a conversion status word rate is fEOSC/20510. output. The conversion status can be observed by pulling CSADC low.
U U W FU CTIO AL BLOCK DIAGRA
V INTERNAL CC OSCILLATOR GND AUTOCALIBRATION F AND CONTROL O CH0 (INT/EXT) CH1 CH2 CH3 CH4 CH5 ∫ ∫ ∫ CH6 8-CHANNEL MUX SDO CH7 SERIAL ∑ ADC SCK INTERFACE ZSSET CSADC FSSET DECIMATING FIR CSMUX CHANNEL DAC D SELECT IN CLK 24248 BD
TEST CIRCUITS
VCC 3.4k SDO SDO 3.4k CLOAD = 20pF CLOAD = 20pF Hi-Z TO VOH Hi-Z TO VOL VOL TO VOH VOH TO VOL V 24248 TC01 OH TO Hi-Z V 24248 TC02 OL TO Hi-Z 10
U U U PIN FUNCTIONS CSADC (Pin 23):
ADC Chip Select Input. A low on this pin
SCK (Pin 25):
Shift Clock for Data Out. This clock synchro- enables the SDO digital output and following each conver- nizes the serial data transfer of the ADC data output. Data sion, the ADC automatically enters the Sleep mode and is shifted out of SDO on the falling edge of SCK. For normal remains in a low power state as long as CSADC is high. If operation, drive this pin in parallel with CLK. CSADC is low during the sleep state, the device draws
F
normal power. A high on this pin also disables the SDO
O (Pin 26):
Digital input which controls the ADC’s notch frequencies and conversion time. When the F digital output. A low-to-high transition on CSADC during O pin is connected to V the Data Output state aborts the data transfer and starts a CC (FO = VCC), the converter uses its internal oscillator and the digital filter first null is located at 50Hz. new conversion. For normal operation, drive this pin in When the F parallel with CSMUX. O pin is connected to GND (FO = OV), the converter uses its internal oscillator and the digital filter
SDO (Pin 24):
Three-State Digital Output. During the data first null is located at 60Hz. When FO is driven by an output period this pin is used for serial data output. When external clock signal with a frequency fEOSC, the converter the chip select CSADC is high (CSADC = VCC), the SDO pin uses this signal as its clock and the digital filter first null is is in a high impedance state. During the Conversion and located at a frequency fEOSC/2560. The resulting output Sleep periods, this pin can be used as a conversion status word rate is fEOSC/20510. output. The conversion status can be observed by pulling CSADC low.
U U W FU CTIO AL BLOCK DIAGRA
V INTERNAL CC OSCILLATOR GND AUTOCALIBRATION F AND CONTROL O CH0 (INT/EXT) CH1 CH2 CH3 CH4 CH5 ∫ ∫ ∫ CH6 8-CHANNEL MUX SDO CH7 SERIAL ∑ ADC SCK INTERFACE ZSSET CSADC FSSET DECIMATING FIR CSMUX CHANNEL DAC D SELECT IN CLK 24248 BD
TEST CIRCUITS
VCC 3.4k SDO SDO 3.4k CLOAD = 20pF CLOAD = 20pF Hi-Z TO VOH Hi-Z TO VOL VOL TO VOH VOH TO VOL V 24248 TC01 OH TO Hi-Z V 24248 TC02 OL TO Hi-Z 10
