Datasheet LTC2442 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 24-Bit High Speed 4-Channel ΔΣ ADC with Integrated Amplifier |
| Pages / Page | 32 / 5 — TIMING CHARACTERISTICS The. denotes the specifications which apply over … |
| File Format / Size | PDF / 397 Kb |
| Document Language | English |
TIMING CHARACTERISTICS The. denotes the specifications which apply over the full operating temperature
Model Line for this Datasheet
Text Version of Document
LTC2442
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fEOSC External Oscillator Frequency Range l 0.1 12 MHz tHEO External Oscillator High Period l 25 10000 ns tLEO External Oscillator Low Period l 25 10000 ns tCONV Conversion Time OSR = 256 (SDI = 0) l 0.99 1.13 1.33 ms OSR = 32768 (SDI = 1) l 126 145 170 ms External Oscillator, 1x Mode l 40 • OSR + 178 ms (Notes 10, 13) fEOSC (KHz) fISCK Internal SCK Frequency Internal Oscillator (Note 9) l 0.8 0.9 1 MHz External Oscillator (Notes 9, 10) fEOSC/10 Hz DISCK Internal SCK Duty Cycle (Note 9) l 45 55 % fESCK External SCK Frequency Range (Note 8) l 20 MHz fLESCK External SCK Low Period (Note 8) l 25 ns tHESCK External SCK High Period (Note 8) l 25 ns tDOUT_ISCK Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 9, 11) l 30.9 35.3 41.6 µs External Oscillator (Notes 9, 10) l 320/fEOSC s tDOUT_ESCK External SCK 32-Bit Data Output Time (Note 8) l 32/fESCK s t1 CS ↓ to SDO Low Z (Note 12) l 0 25 ns t2 CS ↑ to SDO High Z (Note 12) l 0 25 ns t3 CS ↓ to SCK ↓ (Note 9) 5 µs t4 CS ↓ to SCK ↑ (Note 8, 12) l 25 ns tKQMAX SCK ↓ to SDO Valid l 25 ns tKQMIN SDO Hold After SCK ↓ (Note 5) l 15 ns t5 SCK Setup Before CS ↓ l 50 ns t6 SCK Hold After CS ↓ l 50 ns t7 SDI Setup Before SCK ↑ (Note 5) l 10 ns t8 SDI Hold After SCK ↑ (Note 5) l 10 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 8:
The converter is in external SCK mode of operation such that the may cause permanent damage to the device. Exposure to any Absolute SCK pin is used as a digital input. The frequency of the clock signal driving Maximum Rating condition for extended periods may affect device SCK during the data output is fESCK and is expressed in Hz. reliability and lifetime.
Note 9:
The converter is in internal SCK mode of operation such that the
Note 2:
All voltage values are with respect to GND. SCK pin is used as a digital output. In this mode of operation, the SCK pin
Note 3:
VCC = 4.5V to 5.5V unless otherwise specified. has a total equivalent load capacitance of CLOAD = 20pF. VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2;
Note 10:
The external oscillator is connected to the FO pin. The external VIN = SEL+ – SEL–, VINCM = (SEL+ + SEL–)/2. oscillator frequency, fEOSC, is expressed in Hz.
Note 4:
FO pin tied to GND or to external conversion clock source with
Note 11:
The converter uses the internal oscillator. FO = 0V. fEOSC = 10MHz unless otherwise specified.
Note 12:
Guaranteed by design and test correlation.
Note 5:
Guaranteed by design, not subject to test.
Note 13:
There is an internal reset that adds an additional 5 to 15 fO cycles
Note 6:
Integral nonlinearity is defined as the deviation of a code from a to the conversion time. straight line passing through the actual endpoints of the transfer curve.
Note 14:
In order to achieve optimum linearity, the amplifier power The deviation is measured from the center of the quantization band. positive supply input (V+) must exceed the maximum input voltage level by
Note 7:
The converter uses the internal oscillator. 2V or greater. The negative amplifier power supply input (V–) must be at least 200mV below the minimum input voltage level.
Note 15:
Amplifiers are externally compensated with 0.1µF. 2442fb For more information www.linear.com/LTC2442 5
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fEOSC External Oscillator Frequency Range l 0.1 12 MHz tHEO External Oscillator High Period l 25 10000 ns tLEO External Oscillator Low Period l 25 10000 ns tCONV Conversion Time OSR = 256 (SDI = 0) l 0.99 1.13 1.33 ms OSR = 32768 (SDI = 1) l 126 145 170 ms External Oscillator, 1x Mode l 40 • OSR + 178 ms (Notes 10, 13) fEOSC (KHz) fISCK Internal SCK Frequency Internal Oscillator (Note 9) l 0.8 0.9 1 MHz External Oscillator (Notes 9, 10) fEOSC/10 Hz DISCK Internal SCK Duty Cycle (Note 9) l 45 55 % fESCK External SCK Frequency Range (Note 8) l 20 MHz fLESCK External SCK Low Period (Note 8) l 25 ns tHESCK External SCK High Period (Note 8) l 25 ns tDOUT_ISCK Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 9, 11) l 30.9 35.3 41.6 µs External Oscillator (Notes 9, 10) l 320/fEOSC s tDOUT_ESCK External SCK 32-Bit Data Output Time (Note 8) l 32/fESCK s t1 CS ↓ to SDO Low Z (Note 12) l 0 25 ns t2 CS ↑ to SDO High Z (Note 12) l 0 25 ns t3 CS ↓ to SCK ↓ (Note 9) 5 µs t4 CS ↓ to SCK ↑ (Note 8, 12) l 25 ns tKQMAX SCK ↓ to SDO Valid l 25 ns tKQMIN SDO Hold After SCK ↓ (Note 5) l 15 ns t5 SCK Setup Before CS ↓ l 50 ns t6 SCK Hold After CS ↓ l 50 ns t7 SDI Setup Before SCK ↑ (Note 5) l 10 ns t8 SDI Hold After SCK ↑ (Note 5) l 10 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 8:
The converter is in external SCK mode of operation such that the may cause permanent damage to the device. Exposure to any Absolute SCK pin is used as a digital input. The frequency of the clock signal driving Maximum Rating condition for extended periods may affect device SCK during the data output is fESCK and is expressed in Hz. reliability and lifetime.
Note 9:
The converter is in internal SCK mode of operation such that the
Note 2:
All voltage values are with respect to GND. SCK pin is used as a digital output. In this mode of operation, the SCK pin
Note 3:
VCC = 4.5V to 5.5V unless otherwise specified. has a total equivalent load capacitance of CLOAD = 20pF. VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2;
Note 10:
The external oscillator is connected to the FO pin. The external VIN = SEL+ – SEL–, VINCM = (SEL+ + SEL–)/2. oscillator frequency, fEOSC, is expressed in Hz.
Note 4:
FO pin tied to GND or to external conversion clock source with
Note 11:
The converter uses the internal oscillator. FO = 0V. fEOSC = 10MHz unless otherwise specified.
Note 12:
Guaranteed by design and test correlation.
Note 5:
Guaranteed by design, not subject to test.
Note 13:
There is an internal reset that adds an additional 5 to 15 fO cycles
Note 6:
Integral nonlinearity is defined as the deviation of a code from a to the conversion time. straight line passing through the actual endpoints of the transfer curve.
Note 14:
In order to achieve optimum linearity, the amplifier power The deviation is measured from the center of the quantization band. positive supply input (V+) must exceed the maximum input voltage level by
Note 7:
The converter uses the internal oscillator. 2V or greater. The negative amplifier power supply input (V–) must be at least 200mV below the minimum input voltage level.
Note 15:
Amplifiers are externally compensated with 0.1µF. 2442fb For more information www.linear.com/LTC2442 5
