Datasheet LTC2446, LTC2447 (Analog Devices) - 9

LTC2446/LTC2447
APPLICATIONS INFORMATION
rapidly. Within these limits, the LTC2446/LTC2447 Bit 31 (first output bit) is the end of conversion (EOC) convert the bipolar differential input signal, VIN = IN+ – indicator. This bit is available at the SDO pin during the IN – (where IN+ and IN– are the selected input channels), conversion and sleep states whenever the CS pin is LOW. from –FS = –0.5 • VREF to +FS = 0.5 • VREF where VREF = This bit is HIGH during the conversion and goes LOW REF+ – REF– (REF+ and REF– are the selected references). when the conversion is complete. Outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. Bit 30 (second output bit) is a dummy bit (DMY) and is always LOW.
MUXOUT/ADCIN
Bit 29 (third output bit) is the conversion result sign There are two differences between the LTC2446 and the indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, LTC2447. The first is the RMS noise performance. For a this bit is LOW. given OSR, the LTC2447 noise level is approximately √2 Bit 28 (fourth output bit) is the most significant bit (MSB) of times lower (0.5 effective bits) than that of the LTC2446. the result. This bit in conjunction with Bit 29 also provides The second difference is the LTC2447 includes MUXOUT/ the underrange or overrange indication. If both Bit 29 and ADCIN pins. These pins enable an external buffer or gain Bit 28 are HIGH, the differential input voltage is above +FS. block to be inserted between the selected input channel of If both Bit 29 and Bit 28 are LOW, the differential input the multiplexer and the input to the ADC. Since the buffer voltage is below –FS. is driven by the output of the multiplexer, only one circuit is The function of these bits is summarized in Table 1. required for all 8 input channels. Additionally, the transpar- ent calibration feature of the LTC244X family automatically
Table 1. LTC2446/LTC2447 Status Bits
removes the offset errors of the external buffer.
BIT 31 BIT 30 BIT 29 BIT 28 INPUT RANGE EOC DMY SIG MSB
In order to achieve optimum performance, the MUXOUT and VIN ≥ 0.5 • VREF 0 0 1 1 ADCIN pins should not be shorted together. In applications 0V ≤ VIN < 0.5 • VREF 0 0 1 0 where the MUXOUT and ADCIN need to be shorted together, –0.5 • VREF ≤ VIN < 0V 0 0 0 1 the LTC2446 should be used because the MUXOUT and VIN < –0.5 • VREF 0 0 0 0 ADCIN are internally connected for optimum performance. Bits 28-5 are the 24-bit conversion result MSB first.
Output Data Format
Bit 5 is the least significant bit (LSB). The LTC2446/LTC2447 serial output data stream is 32 bits long. The first 3 bits represent status information Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 indicating the sign and conversion state. The next 24 bits may be included in averaging or discarded without loss are the conversion result, MSB first. The remaining 5 bits of resolution. are sub LSBs beyond the 24-bit level that may be included Data is shifted out of the SDO pin under control of the in averaging or discarded without loss of resolution. In the serial clock (SCK), see Figure 3. Whenever CS is HIGH, case of ultrahigh resolution modes, more than 24 effective SDO remains high impedance and SCK is ignored. bits of performance are possible (see Table 4). Under these In order to shift the conversion result out of the device, conditions, sub LSBs are included in the conversion result CS must first be driven LOW. EOC is seen at the SDO pin and represent useful information beyond the 24-bit level. of the device once CS is pulled LOW. EOC changes real The third and fourth bit together are also used to indicate time from HIGH to LOW at the completion of a conversion. an underrange condition (the differential input voltage This signal may be used as an interrupt for an external is below –FS) or an overrange condition (the differential microcontroller. Bit 31 (EOC) can be captured on the first input voltage is above +FS). rising edge of SCK. Bit 30 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is- 24467fb For more information www.linear.com/LTC2446 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Test Circuit Timing Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts