Datasheet LTC2451 (Analog Devices) - 9

LTC2451
APPLICATIONS INFORMATION Reference Voltage Range
VCC power should not be removed from the device when the I2C bus is active to avoid loading the I2C bus lines This converter accepts a truly differential external reference through the internal ESD protection diodes. voltage. The voltage range for the REF+ and REF– pins covers the entire operating range of the device (GND to Each device on the I2C bus is recognized by a unique V + – CC). For correct converter operation, VREF – VREF ≥ 2.5V. address stored in that device and can operate either as a transmitter or receiver, depending on the function of The LTC2451 differential reference input range is 2.5V to the device. In addition to transmitters and receivers, VCC. For the simplest operation, REF+ can be shorted to devices can also be considered as masters or slaves when VCC and REF– can be shorted to GND. performing data transfers. A master is the device which
Input Voltage Range
initiates a data transfer on the bus and generates the clock signals to permit that transfer. Devices addressed Ignoring offset and full-scale errors, the converter will by the master are considered a slave. The address of the theoretically output an “all zero” digital result when the LTC2451 is 0010100. input is at V – REF (a zero scale input) and an “all one” digital result when the input is at V + (a full-scale input). In an The LTC2451 can only be addressed as a slave. It can only REF underrange condition, for all input voltages less than the transmit the last conversion result. The serial clock line, voltage corresponding to output code 0, the converter will SCL, is always an input to the LTC2451 and the serial data generate the output code 0. In an overrange condition, line, SDA, is bidirectional. Figure 2 shows the definition for all input voltages greater than the voltage correspond- of the I2C timing. ing to output code 65535, the converter will generate the
The START and STOP Conditions
output code 65535. A START (S) condition is generated by transitioning SDA
I2C INTERFACE
from HIGH to LOW while SCL is HIGH. The bus is consid- ered to be busy after the START condition. When the data The LTC2451 communicates through an I2C interface. The transfer is finished, a STOP (P) condition is generated by I2C interface is a 2-wire open-drain interface supporting transitioning SDA from LOW to HIGH while SCL is pulled multiple devices and masters on a single bus. The con- HIGH. The bus is free after a STOP is generated. START nected devices can only pull the data line (SDA) LOW and and STOP conditions are always generated by the master. never drive it HIGH. SDA is externally connected to the supply through a pull-up resistor. When the data line is When the bus is in use, it stays busy if a repeated START free, it is pulled HIGH through this resistor. Data on the (Sr) is generated instead of a STOP condition. The re- I2C bus can be transferred at rates up to 100k/s in the peated START (Sr) conditions are functionally identical standard mode and up to 400k/s in the fast mode. The to the START (S). SDA t t SU(DAT) tf t r tr LOW tf tHD(SDA) tSP tBUF SCL tHD(STA) tSU(STA) tSU(STO) S tHD(DAT) tHIGH Sr P S 2451 F02
Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
2451fg 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Input And References Power Requirements I2C Inputs And Outputs I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts