Datasheet LTC2452 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Ultra-Tiny, Differential, 16-Bit ΔΣ ADC with SPI Interface |
| Pages / Page | 22 / 7 — applicaTions inForMaTion. Power-Up Sequence. Figure 2. LTC2452 State … |
| File Format / Size | PDF / 491 Kb |
| Document Language | English |
applicaTions inForMaTion. Power-Up Sequence. Figure 2. LTC2452 State Transition Diagram. Ease of Use
Model Line for this Datasheet
- LTC2452CDDB#PBF LTC2452CDDB#TRMPBF LTC2452CDDB#TRMPBF LTC2452CDDB#TRPBF LTC2452CDDB#TRPBF LTC2452CTS8#PBF LTC2452CTS8#TRMPBF LTC2452CTS8#TRMPBF LTC2452CTS8#TRPBF LTC2452CTS8#TRPBF LTC2452IDDB#PBF LTC2452IDDB#TRMPBF LTC2452IDDB#TRMPBF LTC2452IDDB#TRPBF LTC2452IDDB#TRPBF LTC2452ITS8#PBF LTC2452ITS8#TRMPBF LTC2452ITS8#TRMPBF LTC2452ITS8#TRPBF LTC2452ITS8#TRPBF
Text Version of Document
LTC2452
applicaTions inForMaTion
POWER-ON RESET of data appears at the SDO pin following each falling edge detected at the SCK input pin and appears from MSB to CONVERT LSB. The user can reliably latch this data on every rising edge of the external serial clock signal driving the SCK pin (see Figure 3). SLEEP The DATA OUTPUT state concludes in one of two different ways. First, the DATA OUTPUT state operation is completed SCK = LOW once all 16 data bits have been shifted out and the clock NO AND CS = LOW? then goes low. This corresponds to the 16th falling edge of SCK. Second, the DATA OUTPUT state can be aborted YES at any time by a LOW-to-HIGH transition on the CS input. Following either one of these two actions, the LTC2452 will DATA OUTPUT enter the CONVERT state and initiate a new conversion cycle.
Power-Up Sequence
16TH FALLING When the power supply voltage (V NO YES CC) applied to the con- EDGE OF SCK OR 2452 F02 verter is below approximately 2.1V, the ADC performs a CS = HIGH? power-on reset. This feature guarantees the integrity of the conversion result.
Figure 2. LTC2452 State Transition Diagram
When VCC rises above this critical threshold, the converter generates an internal power-on reset (POR) signal for started, this operation can not be aborted except by a low approximately 0.5ms. The POR signal clears all internal power supply condition (VCC < 2.1V) which generates an registers. Following the POR signal, the LTC2452 starts a internal power-on reset signal. conversion cycle and follows the succession of states shown in Figure 2. The first conversion result following POR is After the completion of a conversion, the LTC2452 enters accurate within the specifications of the device if the power the SLEEP state and remains there until both the chip supply voltage VCC is restored within the operating range select and serial clock inputs are low (CS = SCK = LOW). (2.7V to 5.5V) before the end of the POR time interval. Following this condition, the ADC transitions into the DATA OUTPUT state.
Ease of Use
While in the SLEEP state, whenever the chip select input The LTC2452 data output has no latency, filter settling is pulled high (CS = HIGH), the LTC2452’s power supply delay or redundant results associated with the conversion current is reduced to less than 200nA. When the chip select cycle. There is a one-to-one correspondence between the input is pulled low (CS = LOW), and SCK is maintained at a conversion and the output data. Therefore, multiplexing HIGH logic level, the LTC2452 will return to a normal power multiple analog input voltages requires no special actions. consumption level. During the SLEEP state, the result of the last conversion is held indefinitely in a static register. The LTC2452 performs offset calibrations every conver- sion. This calibration is transparent to the user and has Upon entering the DATA OUTPUT state, SDO outputs the no effect upon the cyclic operation described previously. sign (D15) of the conversion result. During this state, The advantage of continuous calibration is stability of the the ADC shifts the conversion result serially through the ADC performance with respect to time and temperature. SDO output pin under the control of the SCK input pin. There is no latency in generating this data and the result The LTC2452 includes a proprietary input sampling scheme corresponds to the last completed conversion. A new bit that reduces the average input current by several orders 2452fd For more information www.linear.com/LTC2452 7
applicaTions inForMaTion
POWER-ON RESET of data appears at the SDO pin following each falling edge detected at the SCK input pin and appears from MSB to CONVERT LSB. The user can reliably latch this data on every rising edge of the external serial clock signal driving the SCK pin (see Figure 3). SLEEP The DATA OUTPUT state concludes in one of two different ways. First, the DATA OUTPUT state operation is completed SCK = LOW once all 16 data bits have been shifted out and the clock NO AND CS = LOW? then goes low. This corresponds to the 16th falling edge of SCK. Second, the DATA OUTPUT state can be aborted YES at any time by a LOW-to-HIGH transition on the CS input. Following either one of these two actions, the LTC2452 will DATA OUTPUT enter the CONVERT state and initiate a new conversion cycle.
Power-Up Sequence
16TH FALLING When the power supply voltage (V NO YES CC) applied to the con- EDGE OF SCK OR 2452 F02 verter is below approximately 2.1V, the ADC performs a CS = HIGH? power-on reset. This feature guarantees the integrity of the conversion result.
Figure 2. LTC2452 State Transition Diagram
When VCC rises above this critical threshold, the converter generates an internal power-on reset (POR) signal for started, this operation can not be aborted except by a low approximately 0.5ms. The POR signal clears all internal power supply condition (VCC < 2.1V) which generates an registers. Following the POR signal, the LTC2452 starts a internal power-on reset signal. conversion cycle and follows the succession of states shown in Figure 2. The first conversion result following POR is After the completion of a conversion, the LTC2452 enters accurate within the specifications of the device if the power the SLEEP state and remains there until both the chip supply voltage VCC is restored within the operating range select and serial clock inputs are low (CS = SCK = LOW). (2.7V to 5.5V) before the end of the POR time interval. Following this condition, the ADC transitions into the DATA OUTPUT state.
Ease of Use
While in the SLEEP state, whenever the chip select input The LTC2452 data output has no latency, filter settling is pulled high (CS = HIGH), the LTC2452’s power supply delay or redundant results associated with the conversion current is reduced to less than 200nA. When the chip select cycle. There is a one-to-one correspondence between the input is pulled low (CS = LOW), and SCK is maintained at a conversion and the output data. Therefore, multiplexing HIGH logic level, the LTC2452 will return to a normal power multiple analog input voltages requires no special actions. consumption level. During the SLEEP state, the result of the last conversion is held indefinitely in a static register. The LTC2452 performs offset calibrations every conver- sion. This calibration is transparent to the user and has Upon entering the DATA OUTPUT state, SDO outputs the no effect upon the cyclic operation described previously. sign (D15) of the conversion result. During this state, The advantage of continuous calibration is stability of the the ADC shifts the conversion result serially through the ADC performance with respect to time and temperature. SDO output pin under the control of the SCK input pin. There is no latency in generating this data and the result The LTC2452 includes a proprietary input sampling scheme corresponds to the last completed conversion. A new bit that reduces the average input current by several orders 2452fd For more information www.linear.com/LTC2452 7
