Datasheet LTC2461, LTC2463 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Differential Ultra-Tiny, 16-Bit I2C ΔΣ ADCs with 10ppm/°C Max Precision Reference |
| Pages / Page | 20 / 9 — APPLICATIONS INFORMATION. Figure 3. Output Code vs VIN with VIN = 0 … |
| File Format / Size | PDF / 311 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Figure 3. Output Code vs VIN with VIN = 0 (LTC2463). I2C INTERFACE
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Text Version of Document
LTC2461/LTC2463
APPLICATIONS INFORMATION
VREF and below GND, if the differential input is within the data line is free, it is HIGH. Data on the I2C bus can be ±VREF. As an example (Figure 3), if the user desires to transferred at rates up to 100kbits/s in the Standard-Mode measure a signal slightly below ground, the user could and up to 400kbits/s in the Fast-Mode. set V – + IN = GND. If VIN = GND, the output code would be Upon entering the DATA INPUT/OUTPUT state, SDA outputs approximately 32768. If V + IN = GND – 8LSB = –0.305mV, the sign (D15) of the conversion result. During this state, the output code would be approximately 32760. For ap- the ADC shifts the conversion result serially through the plications that require an input range greater than ±1.25V, SDA output pin under the control of the SCL input pin. please refer to the LTC2453. There is no latency in generating this data and the result corresponds to the last completed conversion. A new bit 20 of data appears at the SDA pin following each falling edge 16 detected at the SCL input pin and appears from MSB to LSB. 12 8 The user can reliably latch this data on every rising edge 4 of the external serial clock signal driving the SCL pin. 0 Each device on the I2C bus is recognized by a unique –4 OUTPUT CODE address stored in that device and can operate either as –8 SIGNALS BELOW a transmitter or receiver, depending on the function of –12 GND the device. In addition to transmitters and receivers, –16 devices can also be considered as masters or slaves when –20 –0.001 –0.005 0 0.005 0.001 0.0015 performing data transfers. A master is the device which V + + IN /VREF 24613 F03 initiates a data transfer on the bus and generates the
+ –
clock signals to permit that transfer. Devices addressed
Figure 3. Output Code vs VIN with VIN = 0 (LTC2463)
by the master are considered a slave. The address of the
I2C INTERFACE
LTC2461/LTC2463 is 0010100 (if A0 is tied to GND) or 1010100 (if A0 is tied to VCC). The LTC2461/LTC2463 communicate through an I2C in- terface. The I2C interface is a 2-wire open-drain interface The LTC2461/LTC2463 can only be addressed as a slave. supporting multiple devices and masters on a single bus. It can only transmit the last conversion result. The serial The connected devices can only pull the data line (SDA) clock line, SCL, is always an input to the LTC2461/LTC2463 LOW and can never drive it HIGH. SDA must be externally and the serial data line SDA is bidirectional. Figure 4 shows connected to the supply through a pull-up resistor. When the definition of the I2C timing. SDA t t SU(DAT) tf t r tr LOW tf tHD(SDA) tSP tBUF SCL tHD(STA) tSU(STA) tSU(STO) S tHD(DAT) tHIGH Sr P S 24613 F04
Figure 4. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
24613fa 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Applications Information Package Description Electrical Characteristics Analog Inputs Power Requirements I2c Inputs and Outputs I2c Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts
APPLICATIONS INFORMATION
VREF and below GND, if the differential input is within the data line is free, it is HIGH. Data on the I2C bus can be ±VREF. As an example (Figure 3), if the user desires to transferred at rates up to 100kbits/s in the Standard-Mode measure a signal slightly below ground, the user could and up to 400kbits/s in the Fast-Mode. set V – + IN = GND. If VIN = GND, the output code would be Upon entering the DATA INPUT/OUTPUT state, SDA outputs approximately 32768. If V + IN = GND – 8LSB = –0.305mV, the sign (D15) of the conversion result. During this state, the output code would be approximately 32760. For ap- the ADC shifts the conversion result serially through the plications that require an input range greater than ±1.25V, SDA output pin under the control of the SCL input pin. please refer to the LTC2453. There is no latency in generating this data and the result corresponds to the last completed conversion. A new bit 20 of data appears at the SDA pin following each falling edge 16 detected at the SCL input pin and appears from MSB to LSB. 12 8 The user can reliably latch this data on every rising edge 4 of the external serial clock signal driving the SCL pin. 0 Each device on the I2C bus is recognized by a unique –4 OUTPUT CODE address stored in that device and can operate either as –8 SIGNALS BELOW a transmitter or receiver, depending on the function of –12 GND the device. In addition to transmitters and receivers, –16 devices can also be considered as masters or slaves when –20 –0.001 –0.005 0 0.005 0.001 0.0015 performing data transfers. A master is the device which V + + IN /VREF 24613 F03 initiates a data transfer on the bus and generates the
+ –
clock signals to permit that transfer. Devices addressed
Figure 3. Output Code vs VIN with VIN = 0 (LTC2463)
by the master are considered a slave. The address of the
I2C INTERFACE
LTC2461/LTC2463 is 0010100 (if A0 is tied to GND) or 1010100 (if A0 is tied to VCC). The LTC2461/LTC2463 communicate through an I2C in- terface. The I2C interface is a 2-wire open-drain interface The LTC2461/LTC2463 can only be addressed as a slave. supporting multiple devices and masters on a single bus. It can only transmit the last conversion result. The serial The connected devices can only pull the data line (SDA) clock line, SCL, is always an input to the LTC2461/LTC2463 LOW and can never drive it HIGH. SDA must be externally and the serial data line SDA is bidirectional. Figure 4 shows connected to the supply through a pull-up resistor. When the definition of the I2C timing. SDA t t SU(DAT) tf t r tr LOW tf tHD(SDA) tSP tBUF SCL tHD(STA) tSU(STA) tSU(STO) S tHD(DAT) tHIGH Sr P S 24613 F04
Figure 4. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
24613fa 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Applications Information Package Description Electrical Characteristics Analog Inputs Power Requirements I2c Inputs and Outputs I2c Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts
