Datasheet LTC2471, LTC2473 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Selectable 208sps/833sps, 16-Bit I2C ΔΣ ADCs with 10ppm/°C Max Precision Reference |
| Pages / Page | 20 / 8 — applicaTions inForMaTion. Power-Up Sequence. Figure 3. Reference Start-Up … |
| File Format / Size | PDF / 496 Kb |
| Document Language | English |
applicaTions inForMaTion. Power-Up Sequence. Figure 3. Reference Start-Up Time vs VREF and
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LTC2471/LTC2473
applicaTions inForMaTion
After the completion of a conversion, the LTC2471/LTC2473 When VCC rises above this critical threshold, the converter enters the SLEEP/NAP state and remains there until a valid generates an internal power-on reset (POR) signal for ap- read/write is acknowledged. Following this condition, the proximately 0.5ms. For proper operation VDD needs to be ADC transitions into the DATA INPUT/OUTPUT state. restored to normal operating range (2.7V to 5.5V) before While in the SLEEP/NAP state, the LTC2471/LTC2473’s the conclusion of the POR cycle. The POR signal clears all converters are powered down. This reduces the supply internal registers. Following the POR signal, the LTC2471/ current by approximately 70%. While in the NAP state LTC2473 start a conversion cycle and follow the succes- the reference remains powered up. The user can power sion of states shown in Figure 2. The reference startup down both the reference and the converter by enabling time following a POR is 12ms (CCOMP = CREFOUT = 0.1μF). the sleep mode during the DATA INPUT/OUTPUT state. The first conversion following power-up will be invalid Once the next conversion is complete with the sleep if the reference voltage has not completely settled (see mode enabled, the SLEEP state is entered and power is Figure 3). The first conversion following power up can be reduced to 2μA (maximum). The reference is powered up discarded using the data abort command or simply read once a valid read/write is acknowledged. The reference and ignored. Depending on the value chosen for CCOMP startup time is 12ms (if the reference and compensation and CREFOUT, the reference startup can take more than capacitor values are both 0.1μF). As the reference and one conversion period, see Figure 3. If the startup time is compensation capacitors are decreased, the startup time less than 1.2ms (833sps output rate) or 4.8ms (208sps is reduced (see Figure 3), but the transition noise increases output rate) then conversions following the first period (see Figure 4). are accurate to the device specifications. If the startup time exceeds 1.2ms or 4.8ms then the user can wait the
Power-Up Sequence
appropriate time or use the fixed conversion period as a startup timer by ignoring results within the unsettled When the power supply voltage (VCC) applied to the con- period. Once the reference has settled, all subsequent verter is below approximately 2.1V, the ADC performs a conversion results are valid. If the user places the device power-on reset. This feature guarantees the integrity of into the sleep mode (SLP = 1, reference powered down) the conversion result. the reference will require a startup time proportional to the value of CCOMP and CREFOUT (see Figure 3). 250 25 200 20 VCC = 2.7V 150 V RMS) 15 VCC = 4.1V 100 TIME (ms) 10 50 TRANSITION NOISE (µ 5 0 VCC = 5.5V –50 0 1 0.1 0.01 0.001 0.0001 0.001 0.01 0.1 1 10 CAPACITANCE (µF) CAPACITANCE (µF) 24713 F03 24713 F04
Figure 3. Reference Start-Up Time vs VREF and Figure 4. Transition Noise RMS vs COMP and Compensation Capacitance Reference Capacitance
24713fb 8 For more information www.linear.com/LTC2471 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Inputs Power Requirements I2C Inputs and Outputs I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts
applicaTions inForMaTion
After the completion of a conversion, the LTC2471/LTC2473 When VCC rises above this critical threshold, the converter enters the SLEEP/NAP state and remains there until a valid generates an internal power-on reset (POR) signal for ap- read/write is acknowledged. Following this condition, the proximately 0.5ms. For proper operation VDD needs to be ADC transitions into the DATA INPUT/OUTPUT state. restored to normal operating range (2.7V to 5.5V) before While in the SLEEP/NAP state, the LTC2471/LTC2473’s the conclusion of the POR cycle. The POR signal clears all converters are powered down. This reduces the supply internal registers. Following the POR signal, the LTC2471/ current by approximately 70%. While in the NAP state LTC2473 start a conversion cycle and follow the succes- the reference remains powered up. The user can power sion of states shown in Figure 2. The reference startup down both the reference and the converter by enabling time following a POR is 12ms (CCOMP = CREFOUT = 0.1μF). the sleep mode during the DATA INPUT/OUTPUT state. The first conversion following power-up will be invalid Once the next conversion is complete with the sleep if the reference voltage has not completely settled (see mode enabled, the SLEEP state is entered and power is Figure 3). The first conversion following power up can be reduced to 2μA (maximum). The reference is powered up discarded using the data abort command or simply read once a valid read/write is acknowledged. The reference and ignored. Depending on the value chosen for CCOMP startup time is 12ms (if the reference and compensation and CREFOUT, the reference startup can take more than capacitor values are both 0.1μF). As the reference and one conversion period, see Figure 3. If the startup time is compensation capacitors are decreased, the startup time less than 1.2ms (833sps output rate) or 4.8ms (208sps is reduced (see Figure 3), but the transition noise increases output rate) then conversions following the first period (see Figure 4). are accurate to the device specifications. If the startup time exceeds 1.2ms or 4.8ms then the user can wait the
Power-Up Sequence
appropriate time or use the fixed conversion period as a startup timer by ignoring results within the unsettled When the power supply voltage (VCC) applied to the con- period. Once the reference has settled, all subsequent verter is below approximately 2.1V, the ADC performs a conversion results are valid. If the user places the device power-on reset. This feature guarantees the integrity of into the sleep mode (SLP = 1, reference powered down) the conversion result. the reference will require a startup time proportional to the value of CCOMP and CREFOUT (see Figure 3). 250 25 200 20 VCC = 2.7V 150 V RMS) 15 VCC = 4.1V 100 TIME (ms) 10 50 TRANSITION NOISE (µ 5 0 VCC = 5.5V –50 0 1 0.1 0.01 0.001 0.0001 0.001 0.01 0.1 1 10 CAPACITANCE (µF) CAPACITANCE (µF) 24713 F03 24713 F04
Figure 3. Reference Start-Up Time vs VREF and Figure 4. Transition Noise RMS vs COMP and Compensation Capacitance Reference Capacitance
24713fb 8 For more information www.linear.com/LTC2471 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Inputs Power Requirements I2C Inputs and Outputs I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts
