Datasheet LTC2482 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 16-Bit ΔΣ ADC with Easy Drive Input Current Cancellation |
| Pages / Page | 32 / 5 — TIMING CHARACTERISTICS. The. denotes the specifi cations which apply over … |
| File Format / Size | PDF / 325 Kb |
| Document Language | English |
TIMING CHARACTERISTICS. The. denotes the specifi cations which apply over the full operating temperature
Model Line for this Datasheet
Text Version of Document
LTC2482
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fEOSC External Oscillator Frequency Range (Note 15) l 10 4000 kHz tHEO External Oscillator High Period l 0.125 100 μs tLEO External Oscillator Low Period l 0.125 100 μs tCONV_1 Conversion Time Simultaneous 50Hz/60Hz l 144.1 146.9 149.9 ms External Oscillator l 41036/fEOSC (in kHz) ms fISCK Internal SCK Frequency Internal Oscillator (Note 10) 38.4 kHz External Oscillator (Notes 10, 11) fEOSC/8 kHz DISCK Internal SCK Duty Cycle (Note 10) l 45 55 % fESCK External SCK Frequency Range (Note 10) l 4000 kHz tLESCK External SCK Low Period (Note 10) l 125 ns tHESCK External SCK High Period (Note 10) l 125 ns tDOUT_ISCK Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 12) l 0.61 0.625 0.64 ms External Oscillator (Notes 10, 11) l 192/fEOSC (in kHz) ms tDOUT_ESCK External SCK 24-Bit Data Output Time (Note 10) l 24/fESCK (in kHz) ms t1 CS↓ to SDO Low l 0 200 ns t2 CS↑ to SDO Hi-Z l 0 200 ns t3 CS↓ to SCKØ (Note 10) l 0 200 ns t4 CS↓ to SCK≠ (Note 10) l 50 ns tKQMAX SCK↓ to SDO Valid l 200 ns tKQMIN SDO Hold After SCK↓ (Note 5) l 15 ns t5 SCK Set-Up Before CS↓ l 50 ns t6 SCK Hold After CS↓ l 50 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 9:
Simultaneous 50Hz/60Hz rejection (internal oscillator) or may cause permanent damage to the device. Exposure to any Absolute fEOSC = 280kHz ±2% (external oscillator). Maximum Rating condition for extended periods may affect device
Note 10:
The SCK can be confi gured in external SCK mode or internal SCK reliability and lifetime. mode. In external SCK mode, the SCK pin is used as digital input and the
Note 2:
All voltage values are with respect to GND. driving clock is fESCK. In internal SCK mode, the SCK pin is used as digital
Note 3:
V output and the output clock signal during the data output is f CC = 2.7V to 5.5V unless otherwise specifi ed: ISCK. V
Note 11:
The external oscillator is connected to the f REFCM = VREF/2, FS = 0.5VREF O pin. The external oscillator frequency, fEOSC, is expressed in kHz. VIN = IN+ – IN–, VIN(CM) = (IN+ + IN–)/2
Note 12:
The converter uses the internal oscillator.
Note 4:
Use internal conversion clock or external conversion clock source with f
Note 13:
The output noise includes the contribution of the internal EOSC = 307.2kHz unless otherwise specifi ed. calibration operations.
Note 5:
Guaranteed by design, not subject to test.
Note 14:
Guaranteed by design and test correlation.
Note 6:
Integral nonlinearity is defi ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve.
Note 15:
Refer to Applications Information section for performance vs The deviation is measured from the center of the quantization band. data rate graphs.
Note 7:
f
Note 16:
For V EOSC = 256kHz ±2% (external oscillator). CC < 3V, VIH is 2.5V for pin fO.
Note 8:
fEOSC = 307.2kHz ±2% (external oscillator). 2482fc 5
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fEOSC External Oscillator Frequency Range (Note 15) l 10 4000 kHz tHEO External Oscillator High Period l 0.125 100 μs tLEO External Oscillator Low Period l 0.125 100 μs tCONV_1 Conversion Time Simultaneous 50Hz/60Hz l 144.1 146.9 149.9 ms External Oscillator l 41036/fEOSC (in kHz) ms fISCK Internal SCK Frequency Internal Oscillator (Note 10) 38.4 kHz External Oscillator (Notes 10, 11) fEOSC/8 kHz DISCK Internal SCK Duty Cycle (Note 10) l 45 55 % fESCK External SCK Frequency Range (Note 10) l 4000 kHz tLESCK External SCK Low Period (Note 10) l 125 ns tHESCK External SCK High Period (Note 10) l 125 ns tDOUT_ISCK Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 12) l 0.61 0.625 0.64 ms External Oscillator (Notes 10, 11) l 192/fEOSC (in kHz) ms tDOUT_ESCK External SCK 24-Bit Data Output Time (Note 10) l 24/fESCK (in kHz) ms t1 CS↓ to SDO Low l 0 200 ns t2 CS↑ to SDO Hi-Z l 0 200 ns t3 CS↓ to SCKØ (Note 10) l 0 200 ns t4 CS↓ to SCK≠ (Note 10) l 50 ns tKQMAX SCK↓ to SDO Valid l 200 ns tKQMIN SDO Hold After SCK↓ (Note 5) l 15 ns t5 SCK Set-Up Before CS↓ l 50 ns t6 SCK Hold After CS↓ l 50 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 9:
Simultaneous 50Hz/60Hz rejection (internal oscillator) or may cause permanent damage to the device. Exposure to any Absolute fEOSC = 280kHz ±2% (external oscillator). Maximum Rating condition for extended periods may affect device
Note 10:
The SCK can be confi gured in external SCK mode or internal SCK reliability and lifetime. mode. In external SCK mode, the SCK pin is used as digital input and the
Note 2:
All voltage values are with respect to GND. driving clock is fESCK. In internal SCK mode, the SCK pin is used as digital
Note 3:
V output and the output clock signal during the data output is f CC = 2.7V to 5.5V unless otherwise specifi ed: ISCK. V
Note 11:
The external oscillator is connected to the f REFCM = VREF/2, FS = 0.5VREF O pin. The external oscillator frequency, fEOSC, is expressed in kHz. VIN = IN+ – IN–, VIN(CM) = (IN+ + IN–)/2
Note 12:
The converter uses the internal oscillator.
Note 4:
Use internal conversion clock or external conversion clock source with f
Note 13:
The output noise includes the contribution of the internal EOSC = 307.2kHz unless otherwise specifi ed. calibration operations.
Note 5:
Guaranteed by design, not subject to test.
Note 14:
Guaranteed by design and test correlation.
Note 6:
Integral nonlinearity is defi ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve.
Note 15:
Refer to Applications Information section for performance vs The deviation is measured from the center of the quantization band. data rate graphs.
Note 7:
f
Note 16:
For V EOSC = 256kHz ±2% (external oscillator). CC < 3V, VIH is 2.5V for pin fO.
Note 8:
fEOSC = 307.2kHz ±2% (external oscillator). 2482fc 5
