Datasheet LTM9012 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | Quad 14-Bit, 125Msps ADC with Integrated Drivers |
| Pages / Page | 28 / 1 — FeaTures. DescripTion. 4-Channel Simultaneous Sampling ADC with. … |
| File Format / Size | PDF / 2.1 Mb |
| Document Language | English |
FeaTures. DescripTion. 4-Channel Simultaneous Sampling ADC with. Integrated, Fixed Gain, Differential Drivers. 68.3dB SNR
Model Line for this Datasheet
Text Version of Document
LTM9012 Quad 14-Bit, 125Msps ADC with Integrated Drivers
FeaTures DescripTion
n
4-Channel Simultaneous Sampling ADC with
The LTM®9012 is a 4-channel, simultaneous sampling
Integrated, Fixed Gain, Differential Drivers
14-bit µModule® analog-to-digital converter (ADC) with n
68.3dB SNR
integrated, fixed gain, differential ADC drivers. The low n
78dB SFDR
noise amplifiers are suitable for single-ended drive and n Low Power: 1.27W Total, 318mW per Channel pulse train signals such as imaging applications. Each n 1.8V ADC Core and 3.3V Analog Input Supply channel includes a lowpass filter between the driver out- n Serial LVDS Outputs: 1 or 2 Bits per Channel put and ADC input. n Shutdown and Nap Modes DC specs include ±1.2LSB INL (typ), ±0.3LSB DNL (typ) n 11.25mm × 15mm BGA Package and no missing codes over temperature. The transition noise is a low 1.2LSBRMS.
applicaTions
The digital outputs are serial LVDS and each channel out- n Industrial Imaging puts two bits at a time (2-lane mode). At lower sampling n Medical Imaging rates there is a one bit option (1-lane mode). The LVDS n Multichannel Data Acquisition drivers have optional internal termination and adjustable n Nondestructive Testing output levels to ensure clean signal integrity. L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of The ENC+ and ENC– inputs may be driven differentially Linear Technology Corporation. All other trademarks are the property of their respective owners. or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An internal clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles.
Typical applicaTion Single-Ended Sensor Digitization LTM9012, 125Msps, 70MHz FFT
3.3V 1.8V 1.8V 0 VCC VDD OVDD LTM9012 –10 14 –20 PIPELINE ADC DATA CHANNEL 1 –30 SERIALIZER ENCODER –40 14 PIPELINE AND –50 IMAGE CHANNEL 2 • ADC LVDS SENSOR –60 DRIVERS FPGA • • –70 14 PIPELINE CHANNEL 3 –80 ADC AMPLITUDE (dBFS) –90 14 CHANNEL 4 –100 PIPELINE ADC FR+ –110 FR– –120 INTERNAL 0 5 10 15 20 25 30 35 40 45 50 55 60 VREF REFERENCE & SUPPLY PLL DCO+ BYPASS CAPACITORS FREQUENCY (MHz) DCO– SCK CS ENC+ ENC– SDI SDO PAR/SER 9012 TA01b 9012 TA01a ENCODE CLOCK 9012fa For more information www.linear.com/LTM9012 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Pin Configuration Table Block Diagram Applications Information Typical Application Package Description Revision History Typical Application Related Parts
FeaTures DescripTion
n
4-Channel Simultaneous Sampling ADC with
The LTM®9012 is a 4-channel, simultaneous sampling
Integrated, Fixed Gain, Differential Drivers
14-bit µModule® analog-to-digital converter (ADC) with n
68.3dB SNR
integrated, fixed gain, differential ADC drivers. The low n
78dB SFDR
noise amplifiers are suitable for single-ended drive and n Low Power: 1.27W Total, 318mW per Channel pulse train signals such as imaging applications. Each n 1.8V ADC Core and 3.3V Analog Input Supply channel includes a lowpass filter between the driver out- n Serial LVDS Outputs: 1 or 2 Bits per Channel put and ADC input. n Shutdown and Nap Modes DC specs include ±1.2LSB INL (typ), ±0.3LSB DNL (typ) n 11.25mm × 15mm BGA Package and no missing codes over temperature. The transition noise is a low 1.2LSBRMS.
applicaTions
The digital outputs are serial LVDS and each channel out- n Industrial Imaging puts two bits at a time (2-lane mode). At lower sampling n Medical Imaging rates there is a one bit option (1-lane mode). The LVDS n Multichannel Data Acquisition drivers have optional internal termination and adjustable n Nondestructive Testing output levels to ensure clean signal integrity. L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of The ENC+ and ENC– inputs may be driven differentially Linear Technology Corporation. All other trademarks are the property of their respective owners. or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An internal clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles.
Typical applicaTion Single-Ended Sensor Digitization LTM9012, 125Msps, 70MHz FFT
3.3V 1.8V 1.8V 0 VCC VDD OVDD LTM9012 –10 14 –20 PIPELINE ADC DATA CHANNEL 1 –30 SERIALIZER ENCODER –40 14 PIPELINE AND –50 IMAGE CHANNEL 2 • ADC LVDS SENSOR –60 DRIVERS FPGA • • –70 14 PIPELINE CHANNEL 3 –80 ADC AMPLITUDE (dBFS) –90 14 CHANNEL 4 –100 PIPELINE ADC FR+ –110 FR– –120 INTERNAL 0 5 10 15 20 25 30 35 40 45 50 55 60 VREF REFERENCE & SUPPLY PLL DCO+ BYPASS CAPACITORS FREQUENCY (MHz) DCO– SCK CS ENC+ ENC– SDI SDO PAR/SER 9012 TA01b 9012 TA01a ENCODE CLOCK 9012fa For more information www.linear.com/LTM9012 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Pin Configuration Table Block Diagram Applications Information Typical Application Package Description Revision History Typical Application Related Parts
