Datasheet LT1575, LT1577 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Ultrafast Transient Response, Low Dropout Regulators Adjustable and Fixed |
| Pages / Page | 20 / 7 — PIN FUNCTIONS. SHDN (Pin 1):. GATE (Pin 6):. VIN (Pin 2):. INEG (Pin 7):. … |
| File Format / Size | PDF / 320 Kb |
| Document Language | English |
PIN FUNCTIONS. SHDN (Pin 1):. GATE (Pin 6):. VIN (Pin 2):. INEG (Pin 7):. GND (Pin 3):. FB (Pin 4):. IPOS (Pin 8):. OUT (Pin 4):
Model Line for this Datasheet
- LT1575CN8#PBF LT1575CN8#PBF LT1575CN8-1.5#PBF LT1575CN8-1.5#PBF LT1575CN8-2.8#PBF LT1575CN8-2.8#PBF LT1575CN8-3.3#PBF LT1575CN8-3.3#PBF LT1575CN8-3.5#PBF LT1575CN8-3.5#PBF LT1575CN8-5#PBF LT1575CN8-5#PBF LT1575CS8#PBF LT1575CS8#PBF LT1575CS8#TRPBF LT1575CS8#TRPBF LT1575CS8-1.5#PBF LT1575CS8-1.5#PBF LT1575CS8-2.8#PBF LT1575CS8-2.8#PBF LT1575CS8-3.3#PBF LT1575CS8-3.3#PBF LT1575CS8-3.5#PBF LT1575CS8-3.5#PBF LT1575CS8-5#PBF LT1575CS8-5#PBF
Text Version of Document
LT1575/LT1577
U U U PIN FUNCTIONS SHDN (Pin 1):
This is a multifunction shutdown pin that sation. The transconductance of the error amplifier is 15 provides GATE drive latchoff capability. A 15µA current millimhos and open-loop voltage gain is typically 84dB. source, that turns on when current limit is activated, Frequency compensation is generally performed with a charges a capacitor placed in series with SHDN to GND series RC network to ground. and performs a current limit time-out function. The pin is
GATE (Pin 6):
This is the output of the error amplifier that also the input to a comparator referenced to VREF (1.21V). drives N-channel MOSFETs with up to 5000pF of “effec- When the pin pulls above VREF, the comparator latches the tive” gate capacitance. The typical open-loop output gate drive to the external MOSFET off. The comparator impedance is 2Ω. When using low input capacitance typically has 100mV of hysteresis and the Shutdown pin MOSFETs (< 1500pF), a small gate resistor of 2Ω to 10Ω can be pulled low to reset the latchoff function. This pin dampens high frequency ringing created by an LC reso- provides overvoltage protection or thermal shutdown nance that is created by the MOSFET gate’s lead induc- protection when driven from various resistor divider tance and input capacitance. The GATE pin delivers up to schemes. 50mA for a few hundred nanoseconds when slewing the
VIN (Pin 2):
This is the input supply for the IC that powers gate of the N-channel MOSFET in response to output load the majority of internal circuitry and provides sufficient current transients. gate drive compliance for the external N-channel MOSFET.
INEG (Pin 7):
This is the negative sense terminal of the The typical supply voltage is 12V with 12.5mA of quiescent current limit amplifier. A small sense resistor is connected current. The maximum operating VIN is 20V and the in series with the drain of the external MOSFET and is minimum operating VIN is set by VOUT + VGS of the connected between the IPOS and INEG pins. A 50mV MOSFET at max. IOUT + 1.6V (worst-case VIN to GATE threshold voltage in conjunction with the sense resistor output swing). value sets the current limit level. The current sense resis-
GND (Pin 3):
Analog Ground. This pin is also the negative tor can be a low value shunt or can be made from a piece sense terminal for the internal 1.21V reference. Connect of PC board trace. If the current limit amplifier is not used, external feedback divider networks that terminate to GND tie the INEG pin to IPOS to defeat current limit. An and frequency compensation components that terminate alternative is to ground the INEG pin. This action disables to GND directly to this pin for best regulation and perfor- the current limit amplifier and additional internal circuitry mance. activates the timer circuit on the SHDN pin if the GATE pin swings to the V
FB (Pin 4):
This is the inverting input of the error amplifier IN rail. This option provides the user with a “sense-less” current limit function. for the adjustable voltage LT1575. The noninverting input is tied to the internal 1.21V reference. Input bias current
IPOS (Pin 8):
This is the positive sense terminal of the for this pin is typically 0.6µA flowing out of the pin. This pin current limit amplifier. Tie this pin directly to the main is normally tied to a resistor divider network to set output input voltage from which the output voltage is regulated. voltage. Tie the top of the external resistor divider directly The typical input voltage is a 5V logic supply. This pin is to the output voltage for best regulation performance. also the input to a comparator on the fixed voltage ver- sions that monitors the input/output differential voltage of
OUT (Pin 4):
This is the inverting input of the error the external MOSFET. If this differential voltage is less than amplifier for the fixed voltage LT1575. The fixed voltage 0.5V, then the SHDN timer is not allowed to start even if the parts contain a precision resistor divider network to set GATE is at the V output voltage. The typical resistor divider current is 1mA IN rail. This allows the regulator to start up normally as the input voltage is ramping up, even with very into the pin. Tie this pin directly to the output voltage for slow ramp rates. best regulation performance.
COMP (Pin 5):
This is the high impedance gain node of the error amplifier and is used for external frequency compen- 7
U U U PIN FUNCTIONS SHDN (Pin 1):
This is a multifunction shutdown pin that sation. The transconductance of the error amplifier is 15 provides GATE drive latchoff capability. A 15µA current millimhos and open-loop voltage gain is typically 84dB. source, that turns on when current limit is activated, Frequency compensation is generally performed with a charges a capacitor placed in series with SHDN to GND series RC network to ground. and performs a current limit time-out function. The pin is
GATE (Pin 6):
This is the output of the error amplifier that also the input to a comparator referenced to VREF (1.21V). drives N-channel MOSFETs with up to 5000pF of “effec- When the pin pulls above VREF, the comparator latches the tive” gate capacitance. The typical open-loop output gate drive to the external MOSFET off. The comparator impedance is 2Ω. When using low input capacitance typically has 100mV of hysteresis and the Shutdown pin MOSFETs (< 1500pF), a small gate resistor of 2Ω to 10Ω can be pulled low to reset the latchoff function. This pin dampens high frequency ringing created by an LC reso- provides overvoltage protection or thermal shutdown nance that is created by the MOSFET gate’s lead induc- protection when driven from various resistor divider tance and input capacitance. The GATE pin delivers up to schemes. 50mA for a few hundred nanoseconds when slewing the
VIN (Pin 2):
This is the input supply for the IC that powers gate of the N-channel MOSFET in response to output load the majority of internal circuitry and provides sufficient current transients. gate drive compliance for the external N-channel MOSFET.
INEG (Pin 7):
This is the negative sense terminal of the The typical supply voltage is 12V with 12.5mA of quiescent current limit amplifier. A small sense resistor is connected current. The maximum operating VIN is 20V and the in series with the drain of the external MOSFET and is minimum operating VIN is set by VOUT + VGS of the connected between the IPOS and INEG pins. A 50mV MOSFET at max. IOUT + 1.6V (worst-case VIN to GATE threshold voltage in conjunction with the sense resistor output swing). value sets the current limit level. The current sense resis-
GND (Pin 3):
Analog Ground. This pin is also the negative tor can be a low value shunt or can be made from a piece sense terminal for the internal 1.21V reference. Connect of PC board trace. If the current limit amplifier is not used, external feedback divider networks that terminate to GND tie the INEG pin to IPOS to defeat current limit. An and frequency compensation components that terminate alternative is to ground the INEG pin. This action disables to GND directly to this pin for best regulation and perfor- the current limit amplifier and additional internal circuitry mance. activates the timer circuit on the SHDN pin if the GATE pin swings to the V
FB (Pin 4):
This is the inverting input of the error amplifier IN rail. This option provides the user with a “sense-less” current limit function. for the adjustable voltage LT1575. The noninverting input is tied to the internal 1.21V reference. Input bias current
IPOS (Pin 8):
This is the positive sense terminal of the for this pin is typically 0.6µA flowing out of the pin. This pin current limit amplifier. Tie this pin directly to the main is normally tied to a resistor divider network to set output input voltage from which the output voltage is regulated. voltage. Tie the top of the external resistor divider directly The typical input voltage is a 5V logic supply. This pin is to the output voltage for best regulation performance. also the input to a comparator on the fixed voltage ver- sions that monitors the input/output differential voltage of
OUT (Pin 4):
This is the inverting input of the error the external MOSFET. If this differential voltage is less than amplifier for the fixed voltage LT1575. The fixed voltage 0.5V, then the SHDN timer is not allowed to start even if the parts contain a precision resistor divider network to set GATE is at the V output voltage. The typical resistor divider current is 1mA IN rail. This allows the regulator to start up normally as the input voltage is ramping up, even with very into the pin. Tie this pin directly to the output voltage for slow ramp rates. best regulation performance.
COMP (Pin 5):
This is the high impedance gain node of the error amplifier and is used for external frequency compen- 7
