Datasheet LT3150 (Analog Devices) - 16

LT3150
U U W U APPLICATIO S I FOR ATIO
P1 = 1/(2 • π • RO • C1) P1 = 1/(2 • π • RO • C1) AVOL = gm1 • RO • (VREF/VOUT) P2 IS A FUNCTION AVOL = gm1 • RO • (VREF/VOUT) P2 IS A FUNCTION Z1 = 1/(2 • π • R1 • C1) OF LOAD CURRENT Z1 = 1/(2 • π • ESR • C OF LOAD CURRENT O) P2 = gm (Q1)/(2 • π • CO) P2 = gm (Q1)/(2 • π • CO) AV1 = g GAIN (dB) m1 • R1 • (VREF/VOUT) AV1 = AVOL • (P1/P2) GAIN (dB) = (gm1 • CO)/(gm(Q1) • C1) ILOAD(MIN) ILOAD(MAX) ILOAD(MIN) ILOAD(MAX) 3150 F04 FREQUENCY (Hz) 3150 F05 FREQUENCY (Hz) MANY HIGH ORDER POLES AND MANY HIGH ORDER POLES AND ZEROS PAST UNITY-GAIN fX ZEROS PAST UNITY-GAIN fX VREF gm(Q1) f gm1 X = gm1 • R1 • • V f OUT 2 • π • CO X = 2 • π • C1
Figure 4. Typical Bode Plot for Figure 5. Typical Bode Plot for Tantalum Low ESR Ceramic Output Capacitors or Electrolytic Output Capacitors
higher unity gain bandwidth crossover frequency, fX. fX pole is necessary to roll off the response. In the case of must be set to a value that provides adequate phase and ceramic output capacitors, capacitor C2 in Figure 4 sets gain margin and this criteria limits the shelf gain value. If this pole in combination with R1. In the case of electrolytic higher shelf gain is required for a given application, then or tantalum output capacitors, some small ceramic ca- increase output capacitance. pacitors in parallel with the main output capacitors usually provide the desired response. In both output capacitor cases, the location of the second pole, P2, is set by the MOSFET’s transconductance, gm(Q1), Finally, look for very high frequency gate oscillations in the and the value of the output capacitor, CO. The output load range of 2MHz to 10MHz. Small MOSFETs with low gate current sets the transconductance of the MOSFET. P2 capacitance are most susceptible to this issue. This oscil- moves as a function of load current and consequently, so lation is typically caused by the MOSFET’s “effective” gate does the unity-gain crossover frequency, fX. Figures 4 and capacitance and the MOSFET’s parasitic source induc- 5 depict this behavior. At very low output currents, P2’s tance resonating. The MOSFET’s source inductance is the location moves to a very low frequency. Therefore, set Z1 sum of the device’s bond wire plus package lead induc- at a low enough frequency to provide adequate phase boost. tance and the PCB trace inductance between the MOSFET’s A temptation is to set Z1’s value equal to P2’s value at source and the actual output capacitors. Although the minimum output load current. The bode plot then exhibits MOSFET’s internal inductance is fixed, proper PCB layout a single pole response at minimum output current. How- techniques minimize the external inductance. Minimize ever, this either makes the “shelf gain” and fX too high for the distance between the MOSFET’s source and the output stability or it makes the small signal settling time very long. decoupling capacitors and run wide planes if possible. Set Z1 above the minimum value for P2 so that at small Connect the top of the feedback divider at the point closest output load currents, the second pole P2 occurs and then to the actual load rather than the MOSFET source. If high Z1 provides phase boost prior to crossing unity gain. frequency oscillations persist, a small value resistor in the range of 1Ω to 50Ω in series with the gate of the MOSFET At the highest load current levels, several poles and zeros typically eliminates this ringing. The inclusion of a gate exist just beyond the unity-gain crossover frequency. resistor may permit the high frequency pole discussed in Sometimes, the gain peaks back above unity and a high the preceding paragraph to be eliminated or fine tuned. frequency, low level oscillation appears. A high frequency 3150f 16