Datasheet LT3150 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Fast Transient Response, Low Input Voltage, Very Low Dropout Linear Regulator Controller |
| Pages / Page | 20 / 7 — PI FU CTIO S. VIN2 (Pin 5):. INEG (Pin 12):. GND (Pin 6):. NC (Pins 7, … |
| File Format / Size | PDF / 265 Kb |
| Document Language | English |
PI FU CTIO S. VIN2 (Pin 5):. INEG (Pin 12):. GND (Pin 6):. NC (Pins 7, 10):. FB2 (Pin 8):. IPOS (Pin 13):. SHDN1 (Pin 14):
Model Line for this Datasheet
Text Version of Document
LT3150
U U U PI FU CTIO S VIN2 (Pin 5):
This is the input supply for the linear regulator
INEG (Pin 12):
This is the negative sense terminal of the control circuitry and provides sufficient gate drive compli- current limit amplifier. A small sense resistor is connected ance for the external N-channel MOSFET. The maximum in series with the drain of the external MOSFET and is operating VIN2 is 20V and the minimum operating VIN2 is connected between the IPOS and INEG pins. A 50mV set by VOUT + (VGS of the MOSFET at max IOUT) + 1.6V threshold voltage in conjunction with the sense resistor (worst-case VIN2 to GATE output swing). value sets the current limit level. The current sense resis- tor can be a low value shunt or can be made from a piece
GND (Pin 6):
Analog Ground. This pin is also the negative of PC board trace. If the current limit amplifier is not used, sense terminal for the internal 1.21V reference. Connect the tie the I LDO regulator external feedback divider network and fre- NEG pin to IPOS to defeat current limit. An alternative is to ground the I quency compensation components that terminate to GND NEG pin. This action disables the current limit amplifier and additional internal circuitry activates directly to this pin for best regulation and performance. Also, the timer circuit on the SHDN2 pin if the GATE pin swings tie this pin directly to SWGND (Pin 2) and GND (Pin 15). to the VIN rail. This option provides the user with a
NC (Pins 7, 10):
No Connect. No R TM SENSE current limit function.
FB2 (Pin 8):
This is the inverting input of the error amplifier
IPOS (Pin 13):
This is the positive sense terminal of the for the linear regulator. The noninverting input is tied to the current limit amplifier. Tie this pin directly to the main internal 1.21V reference. Input bias current for this pin is input voltage from which the output voltage is regulated. typically 0.6µA flowing out of the pin. Tie this pin to a
SHDN1 (Pin 14):
Boost Regulator Shutdown Pin. Tie to 1V resistor divider network to set output voltage. Tie the top or more to enable device. Ground to shut down. This pin of the external resistor divider directly to the output load must not float for proper operation. Connect SHDN1 for best regulation performance. externally as it does not incorporate an internal pull-up or
COMP (Pin 9):
This is the high impedance gain node of the pull-down. error amplifier and is used for external frequency compen-
GND (Pin 15):
Boost Converter Analog Ground. This pin sation. The transconductance of the error amplifier is 15 is also the negative sense terminal for the FB1 1.23V millimhos and open-loop voltage gain is typically 84dB. reference. Connect the external feedback divider net- Frequency compensation is generally performed with a work, which sets the V series RC + C network to ground. IN2 supply voltage and terminates to GND, directly to this pin for best regulation and
GATE (Pin 11):
This is the output of the error amplifier performance. Also, tie this pin directly to SWGND (Pin 2) that drives N-channel MOSFETs with up to 5000pF of and GND (Pin 6). “effective” gate capacitance. The typical open-loop out-
FB1 (Pin 16):
Boost Regulator Feedback Pin. Reference put impedance is 2Ω. When using low input capacitance voltage is 1.23V. Connect resistive divider tap here. MOSFETs (< 1500pF), a small gate resistor of 2Ω to 10Ω Minimize trace area at FB1. Set V dampens high frequency ringing created by an LC reso- OUT = VIN2 according to V nance due to the MOSFET gate’s lead inductance and OUT = 1.23V(1 + R1/R2). input capacitance. The GATE pin delivers up to 50mA for No RSENSE is a trademark of Linear Technology Corporation. a few hundred nanoseconds when slewing the gate of the N-channel MOSFET in response to output load current transients. 3150f 7
U U U PI FU CTIO S VIN2 (Pin 5):
This is the input supply for the linear regulator
INEG (Pin 12):
This is the negative sense terminal of the control circuitry and provides sufficient gate drive compli- current limit amplifier. A small sense resistor is connected ance for the external N-channel MOSFET. The maximum in series with the drain of the external MOSFET and is operating VIN2 is 20V and the minimum operating VIN2 is connected between the IPOS and INEG pins. A 50mV set by VOUT + (VGS of the MOSFET at max IOUT) + 1.6V threshold voltage in conjunction with the sense resistor (worst-case VIN2 to GATE output swing). value sets the current limit level. The current sense resis- tor can be a low value shunt or can be made from a piece
GND (Pin 6):
Analog Ground. This pin is also the negative of PC board trace. If the current limit amplifier is not used, sense terminal for the internal 1.21V reference. Connect the tie the I LDO regulator external feedback divider network and fre- NEG pin to IPOS to defeat current limit. An alternative is to ground the I quency compensation components that terminate to GND NEG pin. This action disables the current limit amplifier and additional internal circuitry activates directly to this pin for best regulation and performance. Also, the timer circuit on the SHDN2 pin if the GATE pin swings tie this pin directly to SWGND (Pin 2) and GND (Pin 15). to the VIN rail. This option provides the user with a
NC (Pins 7, 10):
No Connect. No R TM SENSE current limit function.
FB2 (Pin 8):
This is the inverting input of the error amplifier
IPOS (Pin 13):
This is the positive sense terminal of the for the linear regulator. The noninverting input is tied to the current limit amplifier. Tie this pin directly to the main internal 1.21V reference. Input bias current for this pin is input voltage from which the output voltage is regulated. typically 0.6µA flowing out of the pin. Tie this pin to a
SHDN1 (Pin 14):
Boost Regulator Shutdown Pin. Tie to 1V resistor divider network to set output voltage. Tie the top or more to enable device. Ground to shut down. This pin of the external resistor divider directly to the output load must not float for proper operation. Connect SHDN1 for best regulation performance. externally as it does not incorporate an internal pull-up or
COMP (Pin 9):
This is the high impedance gain node of the pull-down. error amplifier and is used for external frequency compen-
GND (Pin 15):
Boost Converter Analog Ground. This pin sation. The transconductance of the error amplifier is 15 is also the negative sense terminal for the FB1 1.23V millimhos and open-loop voltage gain is typically 84dB. reference. Connect the external feedback divider net- Frequency compensation is generally performed with a work, which sets the V series RC + C network to ground. IN2 supply voltage and terminates to GND, directly to this pin for best regulation and
GATE (Pin 11):
This is the output of the error amplifier performance. Also, tie this pin directly to SWGND (Pin 2) that drives N-channel MOSFETs with up to 5000pF of and GND (Pin 6). “effective” gate capacitance. The typical open-loop out-
FB1 (Pin 16):
Boost Regulator Feedback Pin. Reference put impedance is 2Ω. When using low input capacitance voltage is 1.23V. Connect resistive divider tap here. MOSFETs (< 1500pF), a small gate resistor of 2Ω to 10Ω Minimize trace area at FB1. Set V dampens high frequency ringing created by an LC reso- OUT = VIN2 according to V nance due to the MOSFET gate’s lead inductance and OUT = 1.23V(1 + R1/R2). input capacitance. The GATE pin delivers up to 50mA for No RSENSE is a trademark of Linear Technology Corporation. a few hundred nanoseconds when slewing the gate of the N-channel MOSFET in response to output load current transients. 3150f 7
