Datasheet LTC1844 (Analog Devices) - 8

LTC1844 Series
U U W U APPLICATIO S I FOR ATIO
output current change of 1mA to 100mA is – 4mV typical delay can be much shorter (≈70µs) than initial power-up at VOUT = 1.25V. At VOUT = 5V, load regulation is: time if the shutdown duration is brief (<10ms). The maximum shutdown duration required to allow fast shut- (5V/1.25V)(– 4mV) = –16mV down exit is determined by the capacitor leakage current, Because the ADJ pin is relatively high impedance (depend- thus a low leakage bypass capacitor is recommended. ing on the resistor divider used), stray capacitance at this pin can introduce significant phase shift in the error
Output Capacitance and Transient Response
amplifier loop. The PCB layout should be designed to The LTC1844 regulators are designed to be stable with a absolutely minimize the capacitance seen at the ADJ pin. wide range of output capacitors. The ESR of the output To ensure stability over all operating conditions when capacitor affects stability, most notably with small capaci- utilizing large divider resistors, a small feedforward ca- tors. A minimum output capacitor of 1µF with an ESR of pacitor (≈1000pF) in parallel with the upper divider resis- 0.3Ω or less is recommended to ensure stability. The tor (CFF in Figure 2) is recommended. As an added bonus, LTC1844 is a micropower device and output transient this capacitor will improve transient response. response will be a function of output capacitance. Larger values of output capacitance decrease the peak deviations
Bypass Capacitance and Low Noise Performance
and provide improved transient response for larger load current changes. Note that bypass capacitors used to A bypass capacitor can optionally be connected from the decouple individual components powered by the LTC1844 BYP pin to ground to lower output voltage noise. A good will increase the effective output capacitor value. The quality low leakage capacitor is recommended. This ca- shaded region of Figure 3 defines the region over which pacitor will bypass the input of the error amplifier, provid- the LTC1844 regulators are stable. The maximum ESR ing a low frequency noise pole. The noise pole provided by allowed is 0.3Ω. High ESR tantalum and electrolytic ca- this bypass capacitor will lower the output voltage noise to pacitors may be used, but a low ESR ceramic capacitor as low as 30µVRMS with the addition of a 0.1µF capacitor. must be in parallel at the output. There is no minimum ESR Initial regulator power-up time is inversely proportional to requirement. the size of the bypass capacitor, slowing to 10ms with a Extra consideration must be given to the use of ceramic 0.1µF bypass capacitor and 10µF output capacitor. How- capacitors. Ceramic capacitors are manufactured with a ever, the LTC1844 does not discharge the bypass capaci- variety of dielectrics, each with different behavior across tor when put into shutdown and thus the shutdown exit 0.40 0.35 0.30 ) 0.25 Ω 0.20 ESR ( STABLE REGION 0.15 0.10 0.05 00.33 1 3.3 10 33 100 OUTPUT CAPACITANCE (µF) 1844 F03
Figure 3. Stability
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