Datasheet LT1611 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Inverting 1.4MHz Switching Regulator in 5-Lead SOT-23 |
| Pages / Page | 12 / 4 — PIN FUNCTIONS. SW (Pin 1):. GND (Pin 2):. NFB (Pin 3):. SHDN (Pin 4):. … |
| File Format / Size | PDF / 271 Kb |
| Document Language | English |
PIN FUNCTIONS. SW (Pin 1):. GND (Pin 2):. NFB (Pin 3):. SHDN (Pin 4):. VIN (Pin 5):. BLOCK DIAGRAM. Figure 2. OPERATIO
Model Line for this Datasheet
Text Version of Document
LT1611
U U U PIN FUNCTIONS SW (Pin 1):
Switch Pin. Minimize trace area at this pin to VOUT − 1 2 . 3 keep EMI down. R1= 1 2.3 −
GND (Pin 2):
Ground. Tie directly to local ground plane. + 4 5 . •10 6 R2
NFB (Pin 3):
Negative Feedback Pin. Minimize trace area.
SHDN (Pin 4):
Shutdown Pin. Tie to 1V or more to enable Reference voltage is –1.23V. Connect resistive divider tap device. Ground to shut the device down. here. The suggested value for R2 is 10k. Set R1 and R2 according to:
VIN (Pin 5):
Input Supply Pin. Must be locally bypassed.
W BLOCK DIAGRAM
V V IN 5 IN R5 R6 40k 40k 1 SW + COMPARATOR – A1 g DRIVER m FF – A2 R Q Q3 RC RAMP + S Q1 Q2 Σ GENERATOR x10 CC + VOUT R3 A = 3 0.15Ω 30k 1.4MHz – R1 CPL OSCILLATOR (EXTERNAL) R4 (OPTIONAL) 140k NFB SHDN 3 NFB 4 SHUTDOWN 2 GND R2 (EXTERNAL) 1611 BD
Figure 2 U OPERATIO
The LT1611 combines a current mode, fixed frequency flop and turning off the switch. Output voltage decreases PWM architecture with a –1.23V reference to directly (the magnitude increases) as switch current is increased. regulate negative outputs. Operation can be best under- The output, attenuated by external resistor divider R1 and stood by referring to the block diagram of Figure 2. Q1 and R2, appears at the NFB pin, closing the overall loop. Q2 form a bandgap reference core whose loop is closed Frequency compensation is provided internally by RC and around the output of the converter. The driven reference CC. Transient response can be optimized by the addition of point is the lower end of resistor R4, which normally sits a phase lead capacitor, CPL, in parallel with R1 in applica- at a voltage of –1.23V. As the load current changes, the tions where large value or low ESR output capacitors are NFB pin voltage also changes slightly, driving the output used. of gm amplifier A1. Switch current is regulated directly on As load current is decreased, the switch turns on for a a cycle-to-cycle basis by A1’s output. The flip-flop is set at shorter period each cycle. If the load current is further the beginning of each cycle, turning on the switch. When decreased, the converter will skip cycles to maintain the summation of a signal representing switch current and output voltage regulation. a ramp generator (introduced to avoid subharmonic oscil- lations at duty factors greater than 50%) exceeds the V The LT1611 can work in either of two topologies. The C signal, comparator A2 changes stage, resetting the flip- simpler topology appends a capacitive level shift to a 4
U U U PIN FUNCTIONS SW (Pin 1):
Switch Pin. Minimize trace area at this pin to VOUT − 1 2 . 3 keep EMI down. R1= 1 2.3 −
GND (Pin 2):
Ground. Tie directly to local ground plane. + 4 5 . •10 6 R2
NFB (Pin 3):
Negative Feedback Pin. Minimize trace area.
SHDN (Pin 4):
Shutdown Pin. Tie to 1V or more to enable Reference voltage is –1.23V. Connect resistive divider tap device. Ground to shut the device down. here. The suggested value for R2 is 10k. Set R1 and R2 according to:
VIN (Pin 5):
Input Supply Pin. Must be locally bypassed.
W BLOCK DIAGRAM
V V IN 5 IN R5 R6 40k 40k 1 SW + COMPARATOR – A1 g DRIVER m FF – A2 R Q Q3 RC RAMP + S Q1 Q2 Σ GENERATOR x10 CC + VOUT R3 A = 3 0.15Ω 30k 1.4MHz – R1 CPL OSCILLATOR (EXTERNAL) R4 (OPTIONAL) 140k NFB SHDN 3 NFB 4 SHUTDOWN 2 GND R2 (EXTERNAL) 1611 BD
Figure 2 U OPERATIO
The LT1611 combines a current mode, fixed frequency flop and turning off the switch. Output voltage decreases PWM architecture with a –1.23V reference to directly (the magnitude increases) as switch current is increased. regulate negative outputs. Operation can be best under- The output, attenuated by external resistor divider R1 and stood by referring to the block diagram of Figure 2. Q1 and R2, appears at the NFB pin, closing the overall loop. Q2 form a bandgap reference core whose loop is closed Frequency compensation is provided internally by RC and around the output of the converter. The driven reference CC. Transient response can be optimized by the addition of point is the lower end of resistor R4, which normally sits a phase lead capacitor, CPL, in parallel with R1 in applica- at a voltage of –1.23V. As the load current changes, the tions where large value or low ESR output capacitors are NFB pin voltage also changes slightly, driving the output used. of gm amplifier A1. Switch current is regulated directly on As load current is decreased, the switch turns on for a a cycle-to-cycle basis by A1’s output. The flip-flop is set at shorter period each cycle. If the load current is further the beginning of each cycle, turning on the switch. When decreased, the converter will skip cycles to maintain the summation of a signal representing switch current and output voltage regulation. a ramp generator (introduced to avoid subharmonic oscil- lations at duty factors greater than 50%) exceeds the V The LT1611 can work in either of two topologies. The C signal, comparator A2 changes stage, resetting the flip- simpler topology appends a capacitive level shift to a 4
