Datasheet Linear Technology LT1613 (Linear Technology) - 5
| Manufacturer | Linear Technology |
| Description | 1.4MHz, Single Cell DC/DC Converter in 5-Lead SOT-23 |
| Pages / Page | 12 / 5 — OPERATIO. LAYOUT. Figure 3. Single-Ended Primary Inductance Converter … |
| Revision | S |
| File Format / Size | PDF / 302 Kb |
| Document Language | English |
OPERATIO. LAYOUT. Figure 3. Single-Ended Primary Inductance Converter (SEPIC)
Model Line for this Datasheet
Text Version of Document
LT1613
U OPERATIO LAYOUT
C3 L1A 1µF 22µH VIN The LT1613 switches current at high speed, mandating 4V TO 7V careful attention to layout for proper performance. You + C1 VIN SW L1B 15 22 µF µH D1 will not get advertised performance with careless layouts. LT1613 R1 Figure 2 shows recommended component placement for 100k VOUT SHDN SHDN FB 5V/150mA a boost (step-up) converter. Follow this closely in your GND R2 + C2 32.4k 15µF PCB layout. Note the direct path of the switching loops. C1, C2: AVX TAJA156M016 Input capacitor C1 must be placed close (< 5mm) to the IC C3: TAIYO YUDEN JMK325BJ226MM D1: MOTOROLA MBR0520 package. As little as 10mm of wire or PC trace from C 1613 F03 L1, L2: MURATA LQH3C220 IN to VIN will cause problems such as inability to regulate or
Figure 3. Single-Ended Primary Inductance Converter (SEPIC)
oscillation.
Generates 5V from An Input Voltage Above or Below 5V
The ground terminal of output capacitor C2 should tie close to Pin 2 of the LT1613. Doing this reduces dI/dt in the ground copper which keeps high frequency spikes to a minimum. The DC/DC converter ground should tie to the PC board ground plane at one place only, to avoid intro- L1B L1A + C1 VIN ducing dI/dt in the ground plane. VOUT D1 A SEPIC (single-ended primary inductance converter) C3 + schematic is shown in Figure 3. This converter topology C2 1 5 produces a regulated output voltage that spans (i.e., can 2 be higher or lower than) the output. Recommended com- 3 4 SHUTDOWN ponent placement for a SEPIC is shown in Figure 4. VIAS TO GROUND PLANE R2 R1 GROUND L1 + 1613 F04 C1 VIN VOUT D1
Figure 4. Recommended Component Placement for SEPIC
+ C2 1 5
COMPONENT SELECTION
2
Inductors
3 4 SHUTDOWN VIAS TO GROUND Inductors used with the LT1613 should have a saturation PLANE R2 current rating (where inductance is approximately 70% of zero current inductance) of approximately 0.5A or greater. R1 GROUND DCR of the inductors should be 0.5Ω or less. For boost 1613 F02 converters, inductance should be 4.7µH for input voltage
Figure 2. Recommended Component Placement for Boost
less than 3.3V and 10µH for inputs above 3.3V. When
Converter. Note Direct High Current Paths Using Wide PCB Traces. Minimize Area at Pin 3 (FB). Use Vias to Tie Local
using the device as a SEPIC, either a coupled inductor or
Ground Into System Ground Plane. Use Vias at Location Shown
two separate inductors can be used. If using separate
to Avoid Introducing Switching Currents Into Ground Plane
inductors, 22µH units are recommended for input voltage above 3.3V. Coupled inductors have a beneficial mutual inductance, so a 10µH coupled inductor results in the same ripple current as two 20µH uncoupled units. 5
U OPERATIO LAYOUT
C3 L1A 1µF 22µH VIN The LT1613 switches current at high speed, mandating 4V TO 7V careful attention to layout for proper performance. You + C1 VIN SW L1B 15 22 µF µH D1 will not get advertised performance with careless layouts. LT1613 R1 Figure 2 shows recommended component placement for 100k VOUT SHDN SHDN FB 5V/150mA a boost (step-up) converter. Follow this closely in your GND R2 + C2 32.4k 15µF PCB layout. Note the direct path of the switching loops. C1, C2: AVX TAJA156M016 Input capacitor C1 must be placed close (< 5mm) to the IC C3: TAIYO YUDEN JMK325BJ226MM D1: MOTOROLA MBR0520 package. As little as 10mm of wire or PC trace from C 1613 F03 L1, L2: MURATA LQH3C220 IN to VIN will cause problems such as inability to regulate or
Figure 3. Single-Ended Primary Inductance Converter (SEPIC)
oscillation.
Generates 5V from An Input Voltage Above or Below 5V
The ground terminal of output capacitor C2 should tie close to Pin 2 of the LT1613. Doing this reduces dI/dt in the ground copper which keeps high frequency spikes to a minimum. The DC/DC converter ground should tie to the PC board ground plane at one place only, to avoid intro- L1B L1A + C1 VIN ducing dI/dt in the ground plane. VOUT D1 A SEPIC (single-ended primary inductance converter) C3 + schematic is shown in Figure 3. This converter topology C2 1 5 produces a regulated output voltage that spans (i.e., can 2 be higher or lower than) the output. Recommended com- 3 4 SHUTDOWN ponent placement for a SEPIC is shown in Figure 4. VIAS TO GROUND PLANE R2 R1 GROUND L1 + 1613 F04 C1 VIN VOUT D1
Figure 4. Recommended Component Placement for SEPIC
+ C2 1 5
COMPONENT SELECTION
2
Inductors
3 4 SHUTDOWN VIAS TO GROUND Inductors used with the LT1613 should have a saturation PLANE R2 current rating (where inductance is approximately 70% of zero current inductance) of approximately 0.5A or greater. R1 GROUND DCR of the inductors should be 0.5Ω or less. For boost 1613 F02 converters, inductance should be 4.7µH for input voltage
Figure 2. Recommended Component Placement for Boost
less than 3.3V and 10µH for inputs above 3.3V. When
Converter. Note Direct High Current Paths Using Wide PCB Traces. Minimize Area at Pin 3 (FB). Use Vias to Tie Local
using the device as a SEPIC, either a coupled inductor or
Ground Into System Ground Plane. Use Vias at Location Shown
two separate inductors can be used. If using separate
to Avoid Introducing Switching Currents Into Ground Plane
inductors, 22µH units are recommended for input voltage above 3.3V. Coupled inductors have a beneficial mutual inductance, so a 10µH coupled inductor results in the same ripple current as two 20µH uncoupled units. 5
