Datasheet LT3587 (Analog Devices) - 9

LT3587
OPERATION
All three channels of the LT3587 use a constant frequency, 200mV, the bandgap reference, the start-up bias and the current mode control scheme to provide voltage and/or oscillators are also turned on. The SR latch X3 is set at current regulation at the output. Operation can be best un- the start of each oscillator cycle which turns on the power derstood by referring to the Block Diagram in Figure 1. switch Q3. Q3 turns off based on its own feedback loop, which consists of error amplifi er A5 and PWM comparator If EN/SS1 is pulled higher than 200mV, the bandgap refer- A6. The level at the negative input of A6 is set by the error ence, the start-up bias and the oscillator are turned on. At amplifi er A5, and is an amplifi ed version of the difference the start of each oscillator cycle, the SR latch X1 is set, between the reference voltage of 0.8V and the maximum which turns on the power switch Q1. A voltage proportional of the two feedback voltages at V to the switch current is added to a stabilizing ramp and FB3 and IFB3. A separate comparator (not shown) sets the maximum current limit the resulting sum is fed into the positive terminal of the on Q3. PWM comparator A3. When this voltage exceeds the level at the negative input of A3, the SR latch X1 is reset, turning The IFB3 pin is pulled up internally with a current that off the power switch Q1. The level at the negative input is (1/200) times the load current out of the VOUT3 pin. of A3 is set by the error amplifi er A1, which is simply an Therefore, an external resistor connected from this pin amplifi ed version of the difference between the reference to ground generates a feedback voltage proportional to voltage of 1.22V and the feedback voltage. In this manner, the VOUT3 output load current at the IFB3 pin. When the the error amplifi er sets the correct peak switch current voltage at VFB3 is higher than the voltage at IFB3, the third level to keep the output voltage in regulation. If the error channel regulates to the feedback voltage at VFB3, which in amplifi er output increases, more current is delivered to normal application is a divided down voltage from VOUT3. the output; if it decreases, less current is delivered. In this state, the third channel behaves as a boost voltage regulator. On the other hand if the voltage at I The second channel is an inverting converter. This channel FB3 is higher, the third channel regulates to the feedback voltage at I is also enabled through the EN/SS1 pin. The basic opera- FB3, which therefore regulates the V tion of this second channel is the same as the positive OUT3 output load current to a particular value. In this state, the third channel behaves channel. The SR latch X2 is also set at the start of each as a boost current regulator. oscillator cycle. The power switch Q2 is turned on at the same time as Q1. Q2 turns off based on its own feedback PMOS M1 is used as an output disconnect pass transistor loop, which consists of error amplifi er A2 and PWM for the fi rst channel. M1 disconnects the load (VOUT1) from comparator A4. The reference voltage of this negative the input as long as the voltage between CAP1 and VIN channel is ground. is less than 2.5V (typical) and the voltage between CAP1 and V Voltage clamps (not shown) on the output of the error OUT1 is less than 10V (typ). Similarly, PMOS M3 is used as an output disconnect pass transistor for the third amplifi ers A1 and A2 enforce current limit on Q1 and Q2 channel. M3 disconnects the load (V respectively. OUT3) from the input when the third channel is in shutdown (EN/SS3 voltage Similar to the fi rst channel, the third channel is also a is lower than 200mV) and the voltage between CAP3 and positive boost regulator. If EN/SS3 is pulled higher than VOUT3 is less than 10V (typical). 3587fc 9