Datasheet LTC1775 (Analog Devices) - 10

ManufacturerAnalog Devices
DescriptionHigh Power No RSENSE Current Mode Synchronous Step-Down Switching Regulator
Pages / Page24 / 10 — APPLICATIO S I FOR ATIO. Operating Frequency and Synchronization. Figure …
File Format / SizePDF / 307 Kb
Document LanguageEnglish

APPLICATIO S I FOR ATIO. Operating Frequency and Synchronization. Figure 4. SYNC Clock Waveform. Inductor Value Selection

APPLICATIO S I FOR ATIO Operating Frequency and Synchronization Figure 4 SYNC Clock Waveform Inductor Value Selection

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LTC1775
U U W U APPLICATIO S I FOR ATIO
paid to the resulting thermal issues. Under DC conditions,
Operating Frequency and Synchronization
the maximum power that can be dissipated by a MOSFET The choice of operating frequency and inductor value is a switch limits the current through it: trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing P T – T J MAX ( ) A I MOSFET switching losses, both gate charge loss and DS MAX ( )= = R θ R DS ON ( ) JA DS ON ( ) ρTJ MAX ( ) transition loss. However, lower frequency operation requires more inductance for a given amount of ripple For example, the SUD50N03-10 with TJ(MAX) = 175°C, current. TA =70°, θJA = 30° C/W, RDS(ON) = 0.019Ω, ρTJ(MAX) = 1.8 The internal oscillator runs at a nominal 150kHz frequency can operate with a maximum DC current of 10A. In a when the SYNC pin is left open or connected to ground. switching application, the actual power dissipation is Pulling the SYNC pin above 1.2V will increase the fre- increased by the transition losses and is reduced by the quency by 50%. The oscillator will injection lock to a clock switch duty cycle. When the LTC1775 is operating in signal applied to the SYNC pin with a frequency between continuous mode, the duty cycles for the MOSFETs are: 165kHz and 200kHz. The clock high level must exceed 1.2V for at least 1µs and no longer than 4µs as shown in V Top Duty Cycle OUT = Figure 4. The top MOSFET turn-on will synchronize with VIN the rising edge of the clock. V V Bottom Duty Cycle IN OUT = – VIN 1µs < tON < 4µs 7V The MOSFET power dissipations at maximum output current are: 1.2V  V  2 P OUT = I ( )(ρ ) R TOP O MAX ( ) T(TOP ( ) DS ON )  ( ) VIN  + 2 k ( ) V ( ) I ( ) C ( ) f 1775 F04 IN O MAX ( ) RSS ( ) 0 5µs < t < 6µs  V – V  2
Figure 4. SYNC Clock Waveform
P IN OUT = I ( )(ρ ) R BOT O MAX ( ) T BOT ( ) DS ON )  ( ) VIN 
Inductor Value Selection
Both MOSFETs have I2R losses and the P Given the desired input and output voltages, the inductor TOP equation includes an additional term for transition losses, which are value and operating frequency directly determine the largest at high input voltages. The constant k = 1.7 can be ripple current: used to estimate the amount of transition loss. The bottom V   V  MOSFET losses are greatest at high input voltage or during ∆I OUT OUT L =  1– a short circuit when the duty cycle is nearly 100%. The  f L   VIN  ( )( ) temperature rise of the MOSFETs depends on the effective Lower ripple current reduces losses in the inductor, ESR thermal resistance θJA of the heat sink used in the applica- losses in the output capacitors and output voltage ripple. tion. Check the temperature of the MOSFET when testing Thus, highest efficiency operation is obtained at low applications and use appropriate heat sinking such as frequency with small ripple current. To achieve this, how- board power planes to spread the heat. ever, requires a large inductor. 10