Datasheet LTC3401 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 1A, 3MHz Micropower Synchronous Boost Converter |
| Pages / Page | 16 / 6 — PI FU CTIO S. Rt (Pin 1):. GND (Pin 5):. PGOOD (Pin 6):. MODE/SYNC (Pin … |
| File Format / Size | PDF / 241 Kb |
| Document Language | English |
PI FU CTIO S. Rt (Pin 1):. GND (Pin 5):. PGOOD (Pin 6):. MODE/SYNC (Pin 2):. VOUT (Pin 7):. FB (Pin 8):. VC (Pin 9):. SHDN (Pin 10):
Model Line for this Datasheet
Text Version of Document
LTC3401
U U U PI FU CTIO S Rt (Pin 1):
Timing Resistor to Program the Oscillator from SW to VIN from the IC to eliminate high frequency Frequency. ringing due to the resonant tank of the inductor and SW node capacitance, therefore reducing EMI radiation. f = 3 1010 • Hz OSC
GND (Pin 5):
Signal and Power Ground for the IC. Rt
PGOOD (Pin 6):
Power Good Comparator Output. This
MODE/SYNC (Pin 2):
Burst Mode Select and Oscillator open-drain output is low when VFB < – 9% from its Synchronization. regulation voltage. MODE/SYNC = High. Enable Burst Mode operation. The
VOUT (Pin 7):
Output of the Synchronous Rectifier and inductor peak inductor current will be 1/3 the current Bootstrapped Power Source for the IC. A ceramic capaci- limit value and return to zero current on each cycle. tor of at least 1μF is required and should be located as During Burst Mode operation the operation is variable close to the VOUT and GND pins as possible (Pins 7 and 5). frequency, providing a significant efficiency improve- ment at light loads. It is recommended the Burst Mode
FB (Pin 8):
Feedback Pin. Connect resistor divider tap operation only be entered once the part has started up. here. The output voltage can be adjusted from 2.6V to 5.5V. The feedback reference voltage is typically 1.25V. MODE/SYNC = Low. Disable Burst Mode operation and maintain low noise, constant frequency operation.
VC (Pin 9):
Error Amp Output. A frequency compensation network is connected to this pin to compensate the loop. MODE/SYNC = External CLK. Synchronization of the See the section “Compensating the Feedback Loop” for internal oscillator and Burst Mode operation disable. A guidelines. clock pulse width of 100ns to 2μs is required to synchronize.
SHDN (Pin 10):
Shutdown. Grounding this pin shuts down the IC. Tie to >1V to enable (VIN or digital gate output). To
VIN (Pin 3):
Input Supply Pin. operate with input voltages below 1V once the converter
SW (Pin 4):
Switch Pin. Connect inductor and Schottky has started, a 1M resistor from SHDN to VIN, and a 5M diode here. For applications with output voltages over resistor from SHDN to VOUT will provide sufficient hyster- 4.3V, a Schottky diode is required to ensure that the SW esis During shutdown the output voltage will hold up to VIN pin voltage does not exceed its absolute maximum rating. minus a diode drop due to the body diode of the PMOS Minimize trace length to keep EMI down. For discontinu- synchronous switch. If the application requires a com- ous inductor current, a controlled impedance is placed plete disconnect during shutdown then refer to section “Output Disconnect Circuits”. 3401fb 6
U U U PI FU CTIO S Rt (Pin 1):
Timing Resistor to Program the Oscillator from SW to VIN from the IC to eliminate high frequency Frequency. ringing due to the resonant tank of the inductor and SW node capacitance, therefore reducing EMI radiation. f = 3 1010 • Hz OSC
GND (Pin 5):
Signal and Power Ground for the IC. Rt
PGOOD (Pin 6):
Power Good Comparator Output. This
MODE/SYNC (Pin 2):
Burst Mode Select and Oscillator open-drain output is low when VFB < – 9% from its Synchronization. regulation voltage. MODE/SYNC = High. Enable Burst Mode operation. The
VOUT (Pin 7):
Output of the Synchronous Rectifier and inductor peak inductor current will be 1/3 the current Bootstrapped Power Source for the IC. A ceramic capaci- limit value and return to zero current on each cycle. tor of at least 1μF is required and should be located as During Burst Mode operation the operation is variable close to the VOUT and GND pins as possible (Pins 7 and 5). frequency, providing a significant efficiency improve- ment at light loads. It is recommended the Burst Mode
FB (Pin 8):
Feedback Pin. Connect resistor divider tap operation only be entered once the part has started up. here. The output voltage can be adjusted from 2.6V to 5.5V. The feedback reference voltage is typically 1.25V. MODE/SYNC = Low. Disable Burst Mode operation and maintain low noise, constant frequency operation.
VC (Pin 9):
Error Amp Output. A frequency compensation network is connected to this pin to compensate the loop. MODE/SYNC = External CLK. Synchronization of the See the section “Compensating the Feedback Loop” for internal oscillator and Burst Mode operation disable. A guidelines. clock pulse width of 100ns to 2μs is required to synchronize.
SHDN (Pin 10):
Shutdown. Grounding this pin shuts down the IC. Tie to >1V to enable (VIN or digital gate output). To
VIN (Pin 3):
Input Supply Pin. operate with input voltages below 1V once the converter
SW (Pin 4):
Switch Pin. Connect inductor and Schottky has started, a 1M resistor from SHDN to VIN, and a 5M diode here. For applications with output voltages over resistor from SHDN to VOUT will provide sufficient hyster- 4.3V, a Schottky diode is required to ensure that the SW esis During shutdown the output voltage will hold up to VIN pin voltage does not exceed its absolute maximum rating. minus a diode drop due to the body diode of the PMOS Minimize trace length to keep EMI down. For discontinu- synchronous switch. If the application requires a com- ous inductor current, a controlled impedance is placed plete disconnect during shutdown then refer to section “Output Disconnect Circuits”. 3401fb 6
