Datasheet LTC3539, LTC3539-2 (Analog Devices) - 9

LTC3539/LTC3539-2
APPLICATIONS INFORMATION VIN > VOUT Operation COMPONENT SELECTION
The LTC3539 will maintain output voltage regulation even
Inductor Selection
when the input voltage is above the desired output. Note that the efficiency and the maximum output current capability The LTC3539 can utilize small surface mount and chip are reduced. Refer to Typical Performance Characteristics. inductors due to the high switching frequency. Inductor values between 3.3µH and 4.7µH for the LTC3539 and
Short-Circuit Protection
between 1.5µH and 2.5µH for the LTC3539-2 are suitable The LTC3539 output disconnect feature allows an output for most applications.* Larger values of inductance will short circuit while maintaining a maximum internally set allow slightly greater output current capability (and lower current limit. To reduce power dissipation under short- the Burst Mode threshold) by reducing the inductor ripple circuit conditions, the peak switch current limit is reduced current. However, increasing the inductance above 10µH to 1.4A (typical). will increase size while providing little improvement in output current capability.
Schottky Diode
The minimum inductance value is given by: Although it is not required, adding a Schottky diode from VIN(MIN) • (VOUT(MAX) − VIN(MIN)) SW to V L > OUT will improve efficiency by about 2%. Note that Ripple • V this defeats the output disconnect, V OUT(MAX) • f IN > VOUT operation and short circuit protection features. Where:
PCB LAYOUT GUIDELINES
f = 1 for the LTC3539 or 2 for the LTC3539-2 Ripple = allowable inductor current ripple (Amps The high speed operation of the LTC3539 demands careful peak-to-peak) attention to board layout. A careless layout will result in VIN(MIN) = minimum input voltage reduced performance. Figure 1 shows the recommended VOUT(MAX) = maximum output voltage component placement. A large ground pin copper area will help to lower the die temperature. A multilayer board with The inductor current ripple is typically set for 20% to 40% a separate ground plane is ideal. of the maximum inductor current. High frequency ferrite core inductor materials improve efficiency by reducing frequency dependent power losses compared to cheaper powdered iron types. The inductor should have low ESR LTC3539 (series resistance of the windings) to reduce the I2R power SW 1 8 VOUT losses, and must accommodate the peak inductor current without saturating. Molded chokes and some chip induc- PGND 2 7 MODE tors usually do not have enough core area to support the MINIMIZE GND 3 6 FB TRACE ON FB peak inductor current of 2.6A seen on the LTC3539. To AND SW minimize radiated noise, use a shielded inductor. See Table VIN 4 5 SHDN 1 for suggested suppliers and representative components. + VIN *Single cell applications (VIN < 1.6V) should use a 2.2µH inductor for the LTC3539 MULTIPLE VIAS TO GROUND PLANE 3539 F01
Figure 1. Recommended Component Placement for Single Layer Board
35392fc For more information www.linear.com/3539/3539-2 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Related Parts