Datasheet LTC3729L-6 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | PolyPhase, Synchronous Step-Down Switching Regulator |
| Pages / Page | 28 / 7 — TYPICAL PERFOR A CE CHARACTERISTICS. Current Sense Pin Input Current. … |
| File Format / Size | PDF / 356 Kb |
| Document Language | English |
TYPICAL PERFOR A CE CHARACTERISTICS. Current Sense Pin Input Current. EXTVCC Switch Resistance. Oscillator Frequency
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LTC3729L-6
W U TYPICAL PERFOR A CE CHARACTERISTICS Current Sense Pin Input Current EXTVCC Switch Resistance Oscillator Frequency vs Temperature vs Temperature vs Temperature
35 10 700 VOUT = 5V µA) 600 Ω VPLLFLTR = 2.4V 33 8 500 31 6 400 300 29 4 VPLLFLTR = 0V FREQUENCY (kHz) SWITCH RESISTANCE ( 200 CC 27 2 EXTV 100 CURRENT SENSE INPUT CURRENT ( 25 0 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 – 50 – 25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3729L-6 G23 3729L-6 G24 3729L-6 G25
Undervoltage Lockout Shutdown Latch Thresholds vs Temperature vs Temperature
3.50 4.5 4.0 LATCH ARMING 3.45 3.5 3.40 3.0 LATCHOFF THRESHOLD 2.5 3.35 2.0 3.30 1.5 1.0 UNDERVOLTAGE LOCKOUT (V) 3.25 SHUTDOWN LATCH THRESHOLDS (V) 0.5 3.20 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) 3729L-6 G26 3729L-6 G27
U U U PI FU CTIO S EAIN (Pin 1):
Input to the Error Amplifier that compares 50kΩ. The phase-locked loop will force the rising top gate the feedback voltage to the internal 0.6V reference voltage. signal of controller 1 to be synchronized with the rising This pin is normally connected to a resistive divider from edge of the PLLIN signal. the output of the differential amplifier (DIFFOUT).
PHASMD (Pin 4):
Control Input to Phase Selector which
PLLFLTR (Pin 2):
The Phase-Locked Loop’s Low Pass determines the phase relationships between controller 1, Filter is tied to this pin. Alternatively, this pin can be driven controller 2 and the CLKOUT signal. with an AC or DC voltage source to vary the frequency of
I
the internal oscillator.
TH (Pin 5):
Error Amplifier Output and Switching Regula- tor Compensation Point. Both current comparator’s thresh-
PLLIN (Pin 3):
External Synchronization Input to Phase olds increase with this control voltage. The normal voltage Detector. This pin is internally terminated to SGND with range of this pin is from 0V to 2.4V. sn3729l6 3729l6fs 7
W U TYPICAL PERFOR A CE CHARACTERISTICS Current Sense Pin Input Current EXTVCC Switch Resistance Oscillator Frequency vs Temperature vs Temperature vs Temperature
35 10 700 VOUT = 5V µA) 600 Ω VPLLFLTR = 2.4V 33 8 500 31 6 400 300 29 4 VPLLFLTR = 0V FREQUENCY (kHz) SWITCH RESISTANCE ( 200 CC 27 2 EXTV 100 CURRENT SENSE INPUT CURRENT ( 25 0 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 – 50 – 25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3729L-6 G23 3729L-6 G24 3729L-6 G25
Undervoltage Lockout Shutdown Latch Thresholds vs Temperature vs Temperature
3.50 4.5 4.0 LATCH ARMING 3.45 3.5 3.40 3.0 LATCHOFF THRESHOLD 2.5 3.35 2.0 3.30 1.5 1.0 UNDERVOLTAGE LOCKOUT (V) 3.25 SHUTDOWN LATCH THRESHOLDS (V) 0.5 3.20 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) 3729L-6 G26 3729L-6 G27
U U U PI FU CTIO S EAIN (Pin 1):
Input to the Error Amplifier that compares 50kΩ. The phase-locked loop will force the rising top gate the feedback voltage to the internal 0.6V reference voltage. signal of controller 1 to be synchronized with the rising This pin is normally connected to a resistive divider from edge of the PLLIN signal. the output of the differential amplifier (DIFFOUT).
PHASMD (Pin 4):
Control Input to Phase Selector which
PLLFLTR (Pin 2):
The Phase-Locked Loop’s Low Pass determines the phase relationships between controller 1, Filter is tied to this pin. Alternatively, this pin can be driven controller 2 and the CLKOUT signal. with an AC or DC voltage source to vary the frequency of
I
the internal oscillator.
TH (Pin 5):
Error Amplifier Output and Switching Regula- tor Compensation Point. Both current comparator’s thresh-
PLLIN (Pin 3):
External Synchronization Input to Phase olds increase with this control voltage. The normal voltage Detector. This pin is internally terminated to SGND with range of this pin is from 0V to 2.4V. sn3729l6 3729l6fs 7
