Datasheet LTC3808 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | No RSENSE , Low EMI, Synchronous DC/DC Controller with Output Tracking |
| Pages / Page | 28 / 7 — PI FU CTIO S (DFN/SSOP). PLLLPF (Pin 1/Pin 2):. PGOOD (Pin 4/Pin 5):. VFB … |
| File Format / Size | PDF / 386 Kb |
| Document Language | English |
PI FU CTIO S (DFN/SSOP). PLLLPF (Pin 1/Pin 2):. PGOOD (Pin 4/Pin 5):. VFB (Pin 5/Pin 6):. TH (Pin 6/Pin 7):. RUN (Pin 7/Pin 8):
Model Line for this Datasheet
Text Version of Document
LTC3808
U U U PI FU CTIO S (DFN/SSOP) PLLLPF (Pin 1/Pin 2):
Frequency Set/PLL Lowpass Filter.
PGOOD (Pin 4/Pin 5):
Power Good Output Voltage Moni- When synchronizing to an external clock, this pin serves tor Open-Drain Logic Output. This pin is pulled to ground as the low pass filter point for the phase-locked loop. when the voltage on the feedback pin VFB is not within Normally, a series RC is connected between this pin and ±13.3% of its nominal set point. ground.
VFB (Pin 5/Pin 6):
Feedback Pin. This pin receives the When not synchronizing to an external clock, this pin serves remotely sensed feedback voltage for the controller from as the frequency select input. Tying this pin to GND selects an external resistor divider across the output. 300kHz operation; tying this pin to VIN selects 750kHz
I
operation. Floating this pin selects 550kHz operation.
TH (Pin 6/Pin 7):
Current Threshold and Error Amplifier Compensation Point. Nominal operating range on this pin Connect a 2.2nF capacitor between this pin and GND and is from 0.7V to 2V. The voltage on this pin determines the a 1000pF capacitor between this pin and the SYNC/MODE threshold of the main current comparator. when using spread spectrum modulation operation.
RUN (Pin 7/Pin 8):
Run Control Input. Forcing this pin
SYNC/MODE (Pin 2/Pin 3):
This pin performs four func- below 1.1V shuts down the chip. Driving this pin to VIN or tions: 1) auxiliary winding feedback input, 2) external releasing this pin enables the chip to start-up either by clock synchronization input for phase-locked loop, 3) tracking the external voltage at the TRACK/SS pin or with Burst Mode, pulse skipping or forced continuous mode the internal/external soft-start, all based on the connection select, and 4) enable
spread spectrum
modulation opera- at the TRACK/SS pin. tion in pulse skipping mode. Applying a clock with fre-
IPRG (Pin 8/Pin 10):
Three-State Pin to Select Maximum quency between 250kHz to 750kHz causes the internal Peak Sense Voltage Threshold. This pin selects the maxi- oscillator to phase-lock to the external clock and disables mum allowed voltage drop between the SENSE+ and Burst Mode operation but allows pulse skipping at low SENSE– or SW pins (i.e., the maximum allowed drop load currents. across the sense resistor or the external P-channel To select Burst Mode operation at light loads, tie this pin MOSFET). Tie to VIN, GND or float to select 204mV, 85mV to VIN. Grounding this pin selects forced continuous or 125mV respectively. operation, which allows the inductor current to reverse.
BG (Pin 9/Pin 11):
Bottom (NMOS) Gate Drive Output. Tying this pin to VFB selects pulse skipping mode. In these This pin drives the gate of the external N-channel MOSFET. cases, the frequency of the internal oscillator is set by the This pin has an output swing from GND to SENSE+. voltage on the PLLLPF pin. Tying to a voltage between 1.35V to V
TG (Pin 10/Pin 12):
Top (PMOS) Gate Drive Output. This IN – 0.5V enables spread spectrum modulation operation. In this case, an internal 2.6µA pull-down cur- pin drives the gate of the external P-channel MOSFET. This rent source helps to set the voltage at this pin by tying a pin has an output swing from GND to SENSE+. resistor with appropriate value between this pin and VIN.
SENSE+ (Pin 11/Pin 13):
Positive Input to Differential
Do not leave this pin floating
. Current Comparator. Also powers the gate drivers. Nor-
TRACK/SS (Pin 3/Pin 4):
Tracking Input for the Controller mally connected to the source of the external P-channel or Optional External Soft-Start Input. This pin allows the MOSFET when the sense resistor is not used. Otherwise, start-up of V it is connected to the sense resistor. OUT to “track” the external voltage at this pin using an external resistor divider. Tying this pin to VIN
VIN (Pin 12/Pin 14):
Chip Signal Power Supply. This pin allows VOUT start-up with the internal 1ms soft-start powers the entire chip except for the gate drivers. Exter- clamp. An external soft-start can be programmed by nally filtering this pin with a lowpass RC network (e.g., connecting a capacitor between this pin and ground.
Do
R = 10Ω, C = 1µF) is suggested to minimize noise pickup,
not leave this pin floating
. especially in high load current applications. 3808f 7
U U U PI FU CTIO S (DFN/SSOP) PLLLPF (Pin 1/Pin 2):
Frequency Set/PLL Lowpass Filter.
PGOOD (Pin 4/Pin 5):
Power Good Output Voltage Moni- When synchronizing to an external clock, this pin serves tor Open-Drain Logic Output. This pin is pulled to ground as the low pass filter point for the phase-locked loop. when the voltage on the feedback pin VFB is not within Normally, a series RC is connected between this pin and ±13.3% of its nominal set point. ground.
VFB (Pin 5/Pin 6):
Feedback Pin. This pin receives the When not synchronizing to an external clock, this pin serves remotely sensed feedback voltage for the controller from as the frequency select input. Tying this pin to GND selects an external resistor divider across the output. 300kHz operation; tying this pin to VIN selects 750kHz
I
operation. Floating this pin selects 550kHz operation.
TH (Pin 6/Pin 7):
Current Threshold and Error Amplifier Compensation Point. Nominal operating range on this pin Connect a 2.2nF capacitor between this pin and GND and is from 0.7V to 2V. The voltage on this pin determines the a 1000pF capacitor between this pin and the SYNC/MODE threshold of the main current comparator. when using spread spectrum modulation operation.
RUN (Pin 7/Pin 8):
Run Control Input. Forcing this pin
SYNC/MODE (Pin 2/Pin 3):
This pin performs four func- below 1.1V shuts down the chip. Driving this pin to VIN or tions: 1) auxiliary winding feedback input, 2) external releasing this pin enables the chip to start-up either by clock synchronization input for phase-locked loop, 3) tracking the external voltage at the TRACK/SS pin or with Burst Mode, pulse skipping or forced continuous mode the internal/external soft-start, all based on the connection select, and 4) enable
spread spectrum
modulation opera- at the TRACK/SS pin. tion in pulse skipping mode. Applying a clock with fre-
IPRG (Pin 8/Pin 10):
Three-State Pin to Select Maximum quency between 250kHz to 750kHz causes the internal Peak Sense Voltage Threshold. This pin selects the maxi- oscillator to phase-lock to the external clock and disables mum allowed voltage drop between the SENSE+ and Burst Mode operation but allows pulse skipping at low SENSE– or SW pins (i.e., the maximum allowed drop load currents. across the sense resistor or the external P-channel To select Burst Mode operation at light loads, tie this pin MOSFET). Tie to VIN, GND or float to select 204mV, 85mV to VIN. Grounding this pin selects forced continuous or 125mV respectively. operation, which allows the inductor current to reverse.
BG (Pin 9/Pin 11):
Bottom (NMOS) Gate Drive Output. Tying this pin to VFB selects pulse skipping mode. In these This pin drives the gate of the external N-channel MOSFET. cases, the frequency of the internal oscillator is set by the This pin has an output swing from GND to SENSE+. voltage on the PLLLPF pin. Tying to a voltage between 1.35V to V
TG (Pin 10/Pin 12):
Top (PMOS) Gate Drive Output. This IN – 0.5V enables spread spectrum modulation operation. In this case, an internal 2.6µA pull-down cur- pin drives the gate of the external P-channel MOSFET. This rent source helps to set the voltage at this pin by tying a pin has an output swing from GND to SENSE+. resistor with appropriate value between this pin and VIN.
SENSE+ (Pin 11/Pin 13):
Positive Input to Differential
Do not leave this pin floating
. Current Comparator. Also powers the gate drivers. Nor-
TRACK/SS (Pin 3/Pin 4):
Tracking Input for the Controller mally connected to the source of the external P-channel or Optional External Soft-Start Input. This pin allows the MOSFET when the sense resistor is not used. Otherwise, start-up of V it is connected to the sense resistor. OUT to “track” the external voltage at this pin using an external resistor divider. Tying this pin to VIN
VIN (Pin 12/Pin 14):
Chip Signal Power Supply. This pin allows VOUT start-up with the internal 1ms soft-start powers the entire chip except for the gate drivers. Exter- clamp. An external soft-start can be programmed by nally filtering this pin with a lowpass RC network (e.g., connecting a capacitor between this pin and ground.
Do
R = 10Ω, C = 1µF) is suggested to minimize noise pickup,
not leave this pin floating
. especially in high load current applications. 3808f 7
